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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
llvm-mirror/test/CodeGen
Ahmed Bougacha 3e610ad27b [GlobalISel] Mark newly-created gvregs as having a bank.
Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a testcase that
hit that error and had a size for no reason.

llvm-svn: 276012
2016-07-19 19:48:36 +00:00
..
AArch64 [AARCH64] Fix linu triple typo 2016-07-19 14:12:45 +00:00
AMDGPU AMDGPU: Expand register indexing pseudos in custom inserter 2016-07-19 00:35:03 +00:00
ARM [ARM] Refactor Thumb2 Mul and Mla instr descs 2016-07-19 14:44:05 +00:00
BPF
Generic Move mempcpy_call.ll to X86 subdirectory 2016-07-13 18:28:45 +00:00
Hexagon [Hexagon] Handle returning small structures by value 2016-07-18 17:30:41 +00:00
Inputs
Lanai
Mips [mips] Correct label prefixes for N32 and N64. 2016-07-19 10:49:03 +00:00
MIR [GlobalISel] Mark newly-created gvregs as having a bank. 2016-07-19 19:48:36 +00:00
MSP430
NVPTX [NVPTX] Make sure we adjust alignment at all call sites 2016-07-18 21:58:48 +00:00
PowerPC [PowerPC] Remove redundant direct moves when extracting integers and converting to FP 2016-07-18 15:30:00 +00:00
SPARC
SystemZ [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities 2016-07-11 18:45:03 +00:00
Thumb [Thumb-1] Select post-increment load and store where possible 2016-07-15 08:03:56 +00:00
Thumb2
WebAssembly
WinEH
X86 [X86][AVX512] Added AVX512 subvector broadcast tests 2016-07-19 17:04:28 +00:00
XCore