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123 lines
3.2 KiB
LLVM
123 lines
3.2 KiB
LLVM
; Test 32-bit atomic exchange.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check register exchange.
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define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f1:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: cs %r2, %r4, 0(%r3)
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; CHECK: jlh [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw xchg i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CS range.
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define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f2:
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; CHECK: l %r2, 4092(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1023
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which requires CSY.
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define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f3:
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; CHECK: ly %r2, 4096(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1024
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CSY range.
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define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f4:
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; CHECK: ly %r2, 524284(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which needs separate address logic.
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f5:
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; CHECK: agfi %r3, 524288
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the negative aligned CSY range.
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define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f6:
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; CHECK: ly %r2, -4(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the low end of the CSY range.
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define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f7:
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; CHECK: ly %r2, -524288(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word down, which needs separate address logic.
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define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f8:
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; CHECK: agfi %r3, -524292
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check that indexed addresses are not allowed.
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define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
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; CHECK: f9:
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; CHECK: agr %r3, %r4
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check exchange of a constant. We should force it into a register and
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; use the sequence above.
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define i32 @f10(i32 %dummy, i32 *%src) {
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; CHECK: f10:
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; CHECK: llill [[VALUE:%r[0-9+]]], 40000
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: cs %r2, [[VALUE]], 0(%r3)
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; CHECK: jlh [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw xchg i32 *%src, i32 40000 seq_cst
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ret i32 %res
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}
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