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05f3cb9f0c
This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
# Test z13 instructions that don't have PC-relative operands.
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# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 2>&1 \
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# RUN: | FileCheck %s
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# This would be "vlef %v0, 0, 4", but element 4 is invalid.
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x40 0x03
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0xe7 0x00 0x00 0x00 0x40 0x03
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# ...and again with element 15
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03
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0xe7 0x00 0x00 0x00 0xf0 0x03
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# This would be "vleg %v0, 0, 2", but element 2 is invalid.
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x20 0x02
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0xe7 0x00 0x00 0x00 0x20 0x02
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# ...and again with element 15
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02
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0xe7 0x00 0x00 0x00 0xf0 0x02
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# This would be "vleh %v0, 0, 8", but element 8 is invalid.
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x80 0x01
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0xe7 0x00 0x00 0x00 0x80 0x01
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# ...and again with element 15
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#
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#CHECK: warning: invalid instruction encoding
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#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x01
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0xe7 0x00 0x00 0x00 0xf0 0x01
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