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91 lines
3.0 KiB
C++
91 lines
3.0 KiB
C++
//===- Mem2Reg.cpp - The -mem2reg pass, a wrapper around the Utils lib ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass is a simple pass wrapper around the PromoteMemToReg function call
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// exposed by the Utils library.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Utils/PromoteMemToReg.h"
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#include "llvm/Transforms/Utils/UnifyFunctionExitNodes.h"
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#include "llvm/Analysis/Dominators.h"
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#include "llvm/Instructions.h"
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#include "llvm/Function.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPromoted("mem2reg", "Number of alloca's promoted");
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struct PromotePass : public FunctionPass {
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// runOnFunction - To run this pass, first we calculate the alloca
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// instructions that are safe for promotion, then we promote each one.
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//
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virtual bool runOnFunction(Function &F);
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// getAnalysisUsage - We need dominance frontiers
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//
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DominatorTree>();
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AU.addRequired<DominanceFrontier>();
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AU.addRequired<TargetData>();
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AU.setPreservesCFG();
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// This is a cluster of orthogonal Transforms
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AU.addPreserved<UnifyFunctionExitNodes>();
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AU.addPreservedID(LowerSelectID);
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AU.addPreservedID(LowerSwitchID);
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AU.addPreservedID(LowerInvokePassID);
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AU.addPreservedID(LowerAllocationsID);
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}
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};
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RegisterOpt<PromotePass> X("mem2reg", "Promote Memory to Register");
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} // end of anonymous namespace
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bool PromotePass::runOnFunction(Function &F) {
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std::vector<AllocaInst*> Allocas;
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const TargetData &TD = getAnalysis<TargetData>();
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BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
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bool Changed = false;
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DominatorTree &DT = getAnalysis<DominatorTree>();
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DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
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while (1) {
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Allocas.clear();
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// Find allocas that are safe to promote, by looking at all instructions in
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// the entry node
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for (BasicBlock::iterator I = BB.begin(), E = --BB.end(); I != E; ++I)
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if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) // Is it an alloca?
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if (isAllocaPromotable(AI, TD))
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Allocas.push_back(AI);
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if (Allocas.empty()) break;
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PromoteMemToReg(Allocas, DT, DF, TD);
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NumPromoted += Allocas.size();
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Changed = true;
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}
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return Changed;
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}
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// Publically exposed interface to pass...
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const PassInfo *llvm::PromoteMemoryToRegisterID = X.getPassInfo();
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// createPromoteMemoryToRegister - Provide an entry point to create this pass.
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//
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FunctionPass *llvm::createPromoteMemoryToRegisterPass() {
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return new PromotePass();
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}
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