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This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> llvm-svn: 168837
361 lines
15 KiB
LLVM
361 lines
15 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing -verify-machineinstrs | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios0.0.0"
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; CHECK: f
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; The vld2 and vst2 are not aligned wrt each other, the second Q loaded is the
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; first one stored.
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; The coalescer must find a super-register larger than QQ to eliminate the copy
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; setting up the vst2 data.
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; CHECK: vld2
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; CHECK-NOT: vorr
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; CHECK-NOT: vmov
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; CHECK: vst2
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define void @f(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
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ret void
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}
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; CHECK: f1
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; FIXME: This function still has copies.
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define void @f1(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
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ret void
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}
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; CHECK: f2
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; FIXME: This function still has copies.
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define void @f2(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
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%c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
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%p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
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%add.ptr = getelementptr inbounds float* %p.addr.0, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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%vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
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%dec = add nsw i32 %c.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end: ; preds = %do.body
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ret void
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}
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declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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; CHECK: f3
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; This function has lane insertions that span basic blocks.
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; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.
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;
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; void f3(float *p, float *q) {
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; float32x2_t x;
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; x[1] = p[3];
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; if (q)
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; x[0] = q[0] + q[1];
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; else
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; x[0] = p[2];
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; vst1_f32(p+4, x);
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; }
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;
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f3(float* %p, float* %q) nounwind ssp {
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entry:
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%arrayidx = getelementptr inbounds float* %p, i32 3
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%0 = load float* %arrayidx, align 4
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%vecins = insertelement <2 x float> undef, float %0, i32 1
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx2 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx2, align 4
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%add = fadd float %1, %2
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%vecins3 = insertelement <2 x float> %vecins, float %add, i32 0
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br label %if.end
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if.else: ; preds = %entry
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%arrayidx4 = getelementptr inbounds float* %p, i32 2
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%3 = load float* %arrayidx4, align 4
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%vecins5 = insertelement <2 x float> %vecins, float %3, i32 0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]
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%add.ptr = getelementptr inbounds float* %p, i32 4
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%4 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind
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declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly
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; CHECK: f4
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; This function inserts a lane into a fully defined vector.
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; The destination lane isn't read, so the subregs can coalesce.
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f4(float* %p, float* %q) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %0, i32 4)
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx1 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx1, align 4
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%add = fadd float %1, %2
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%vecins = insertelement <2 x float> %vld1, float %add, i32 1
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ]
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %0, <2 x float> %x.0, i32 4)
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ret void
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}
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; CHECK: f5
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; Coalesce vector lanes through phis.
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; CHECK: vmov.f32 {{.*}}, #1.0
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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; CHECK: bx
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; We may leave the last insertelement in the if.end block.
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; It is inserting the %add value into a dead lane, but %add causes interference
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; in the entry block, and we don't do dead lane checks across basic blocks.
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define void @f5(float* %p, float* %q) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %0, i32 4)
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%vecext = extractelement <4 x float> %vld1, i32 0
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%vecext1 = extractelement <4 x float> %vld1, i32 1
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%vecext2 = extractelement <4 x float> %vld1, i32 2
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%vecext3 = extractelement <4 x float> %vld1, i32 3
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%add = fadd float %vecext3, 1.000000e+00
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%arrayidx = getelementptr inbounds float* %q, i32 1
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%1 = load float* %arrayidx, align 4
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%add4 = fadd float %vecext, %1
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%2 = load float* %q, align 4
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%add6 = fadd float %vecext1, %2
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%arrayidx7 = getelementptr inbounds float* %q, i32 2
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%3 = load float* %arrayidx7, align 4
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%add8 = fadd float %vecext2, %3
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%a.0 = phi float [ %add4, %if.then ], [ %vecext, %entry ]
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%b.0 = phi float [ %add6, %if.then ], [ %vecext1, %entry ]
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%c.0 = phi float [ %add8, %if.then ], [ %vecext2, %entry ]
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%vecinit = insertelement <4 x float> undef, float %a.0, i32 0
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%vecinit9 = insertelement <4 x float> %vecinit, float %b.0, i32 1
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%vecinit10 = insertelement <4 x float> %vecinit9, float %c.0, i32 2
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%vecinit11 = insertelement <4 x float> %vecinit10, float %add, i32 3
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tail call void @llvm.arm.neon.vst1.v4f32(i8* %0, <4 x float> %vecinit11, i32 4)
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ret void
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}
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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; CHECK: pr13999
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define void @pr13999() nounwind readonly {
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entry:
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br i1 true, label %outer_loop, label %loop.end
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outer_loop:
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%d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
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%0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0
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br i1 undef, label %after_inner_loop, label %inner_loop
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inner_loop:
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br i1 true, label %after_inner_loop, label %inner_loop
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after_inner_loop:
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%1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>,
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%inner_loop ]
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%2 = extractelement <2 x double> %1, i32 1
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%add = fadd double 1.0, %2
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br i1 false, label %loop.end, label %outer_loop
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loop.end:
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%d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
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ret void
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}
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; CHECK: pr14078
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define arm_aapcs_vfpcc i32 @pr14078(i8* nocapture %arg, i8* nocapture %arg1, i32 %arg2) nounwind uwtable readonly {
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bb:
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br i1 undef, label %bb31, label %bb3
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bb3: ; preds = %bb12, %bb
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%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp4 = bitcast <1 x i64> %tmp to <2 x float>
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%tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <4 x i32> zeroinitializer
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%tmp6 = bitcast <4 x float> %tmp5 to <2 x i64>
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%tmp7 = shufflevector <2 x i64> %tmp6, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp8 = bitcast <1 x i64> %tmp7 to <2 x float>
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%tmp9 = tail call <2 x float> @baz(<2 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00>, <2 x float> %tmp8, <2 x float> zeroinitializer) nounwind
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br i1 undef, label %bb10, label %bb12
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bb10: ; preds = %bb3
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%tmp11 = load <4 x float>* undef, align 8
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br label %bb12
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bb12: ; preds = %bb10, %bb3
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%tmp13 = shufflevector <2 x float> %tmp9, <2 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%tmp14 = bitcast <2 x float> %tmp13 to <1 x i64>
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%tmp15 = shufflevector <1 x i64> %tmp14, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>
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%tmp16 = bitcast <2 x i64> %tmp15 to <4 x float>
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%tmp17 = fmul <4 x float> zeroinitializer, %tmp16
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%tmp18 = bitcast <4 x float> %tmp17 to <2 x i64>
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%tmp19 = shufflevector <2 x i64> %tmp18, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp20 = bitcast <1 x i64> %tmp19 to <2 x float>
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%tmp21 = tail call <2 x float> @baz67(<2 x float> %tmp20, <2 x float> undef) nounwind
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%tmp22 = tail call <2 x float> @baz67(<2 x float> %tmp21, <2 x float> %tmp21) nounwind
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%tmp23 = shufflevector <2 x float> %tmp22, <2 x float> undef, <4 x i32> zeroinitializer
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%tmp24 = bitcast <4 x float> %tmp23 to <2 x i64>
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%tmp25 = shufflevector <2 x i64> %tmp24, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp26 = bitcast <1 x i64> %tmp25 to <2 x float>
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%tmp27 = extractelement <2 x float> %tmp26, i32 0
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%tmp28 = fcmp olt float %tmp27, 0.000000e+00
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%tmp29 = select i1 %tmp28, i32 0, i32 undef
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%tmp30 = icmp ult i32 undef, %arg2
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br i1 %tmp30, label %bb3, label %bb31
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bb31: ; preds = %bb12, %bb
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%tmp32 = phi i32 [ 1, %bb ], [ %tmp29, %bb12 ]
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ret i32 %tmp32
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}
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declare <2 x float> @baz(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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declare <2 x float> @baz67(<2 x float>, <2 x float>) nounwind readnone
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%struct.wombat.5 = type { %struct.quux, %struct.quux, %struct.quux, %struct.quux }
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%struct.quux = type { <4 x float> }
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; CHECK: pr14079
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define linkonce_odr arm_aapcs_vfpcc %struct.wombat.5 @pr14079(i8* nocapture %arg, i8* nocapture %arg1, i8* nocapture %arg2) nounwind uwtable inlinehint {
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bb:
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%tmp = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp3 = bitcast <1 x i64> %tmp to <2 x float>
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%tmp4 = shufflevector <2 x float> %tmp3, <2 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <2 x i32> <i32 1, i32 3>
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%tmp6 = bitcast <2 x float> %tmp5 to <1 x i64>
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%tmp7 = shufflevector <1 x i64> undef, <1 x i64> %tmp6, <2 x i32> <i32 0, i32 1>
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%tmp8 = bitcast <2 x i64> %tmp7 to <4 x float>
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%tmp9 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> <i32 1>
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%tmp10 = bitcast <1 x i64> %tmp9 to <2 x float>
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%tmp11 = shufflevector <2 x float> %tmp10, <2 x float> undef, <2 x i32> <i32 0, i32 2>
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%tmp12 = shufflevector <2 x float> %tmp11, <2 x float> undef, <2 x i32> <i32 0, i32 2>
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%tmp13 = bitcast <2 x float> %tmp12 to <1 x i64>
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%tmp14 = shufflevector <1 x i64> %tmp13, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%tmp15 = bitcast <2 x i64> %tmp14 to <4 x float>
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%tmp16 = insertvalue %struct.wombat.5 undef, <4 x float> %tmp8, 1, 0
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%tmp17 = insertvalue %struct.wombat.5 %tmp16, <4 x float> %tmp15, 2, 0
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%tmp18 = insertvalue %struct.wombat.5 %tmp17, <4 x float> undef, 3, 0
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ret %struct.wombat.5 %tmp18
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}
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; CHECK: adjustCopiesBackFrom
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; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom
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; is tempted to remove it.
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; CHECK: %if.else3
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; CHECK: vorr d
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define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) {
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entry:
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%0 = extractelement <2 x i64> %in, i32 0
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%cmp = icmp slt i64 %0, 1
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%.in = select i1 %cmp, <2 x i64> <i64 0, i64 undef>, <2 x i64> %in
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%1 = extractelement <2 x i64> %in, i32 1
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%cmp1 = icmp slt i64 %1, 1
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br i1 %cmp1, label %if.then2, label %if.else3
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if.then2: ; preds = %entry
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%2 = insertelement <2 x i64> %.in, i64 0, i32 1
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br label %if.end4
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if.else3: ; preds = %entry
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%3 = shufflevector <2 x i64> %.in, <2 x i64> %in, <2 x i32> <i32 0, i32 3>
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br label %if.end4
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if.end4: ; preds = %if.else3, %if.then2
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%result.2 = phi <2 x i64> [ %2, %if.then2 ], [ %3, %if.else3 ]
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store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128
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ret void
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}
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; <rdar://problem/12758887>
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; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than
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; once under rare circumstances. When widening a register from QPR to DTriple
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; with the original virtual register in dsub_1_dsub_2, the double rewrite would
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; produce an invalid sub-register.
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;
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; This is because dsub_1_dsub_2 is not an idempotent sub-register index.
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; It will translate %vr:dsub_0 -> %vr:dsub_1.
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define hidden fastcc void @radar12758887() nounwind optsize ssp {
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entry:
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br i1 undef, label %for.body, label %for.end70
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for.body: ; preds = %for.end, %entry
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br i1 undef, label %for.body29, label %for.end
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for.body29: ; preds = %for.body29, %for.body
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%0 = load <2 x double>* null, align 1
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%splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
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%mul41 = fmul <2 x double> undef, %splat40
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%add42 = fadd <2 x double> undef, %mul41
|
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%splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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%mul45 = fmul <2 x double> undef, %splat44
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%add46 = fadd <2 x double> undef, %mul45
|
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br i1 undef, label %for.end, label %for.body29
|
|
|
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for.end: ; preds = %for.body29, %for.body
|
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%accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]
|
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%accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]
|
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%1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0>
|
|
%add58 = fadd <2 x double> undef, %1
|
|
%mul61 = fmul <2 x double> %add58, undef
|
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%add63 = fadd <2 x double> undef, %mul61
|
|
%add64 = fadd <2 x double> undef, %add63
|
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%add67 = fadd <2 x double> undef, %add64
|
|
store <2 x double> %add67, <2 x double>* undef, align 1
|
|
br i1 undef, label %for.end70, label %for.body
|
|
|
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for.end70: ; preds = %for.end, %entry
|
|
ret void
|
|
}
|