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https://github.com/RPCS3/llvm-mirror.git
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6bda113a4e
Summary:
Patch adds support for indexed and unpredicated vectors forms of the
following instructions:
* SMULLB, SMULLT, UMULLB, UMULLT, SQDMULLB, SQDMULLT
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61936
llvm-svn: 361002
107 lines
3.9 KiB
ArmAsm
107 lines
3.9 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// z register out of range for index
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smullt z0.s, z1.h, z8.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: smullt z0.s, z1.h, z8.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.s, z16.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: smullt z0.d, z1.s, z16.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Index out of bounds
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smullt z0.s, z1.h, z7.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: smullt z0.s, z1.h, z7.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.s, z1.h, z7.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: smullt z0.s, z1.h, z7.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.s, z15.s[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: smullt z0.d, z1.s, z15.s[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.s, z15.s[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: smullt z0.d, z1.s, z15.s[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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smullt z0.b, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.b, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.h, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.h, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.s, z0.s, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.s, z0.s, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.d, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.s, z1.b, z2.b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.s, z1.b, z2.b[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.s, z1.s, z2.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.s, z1.s, z2.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.s, z1.d, z2.d[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.s, z1.d, z2.d[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.b, z2.b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.d, z1.b, z2.b[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.h, z2.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.d, z1.h, z2.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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smullt z0.d, z1.d, z2.d[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: smullt z0.d, z1.d, z2.d[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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smullt z31.d, z31.s, z15.s[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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smullt z31.d, z31.s, z15.s[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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