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bea54db865
Add the aarch64[_be]-*-gnu_ilp32 targets to support the GNU ILP32 ABI for AArch64. The needed codegen changes were mostly already implemented in D61259, which added support for the watchOS ILP32 ABI. The main changes are: - Wiring up the new target to enable ILP32 codegen and MC. - ILP32 va_list support. - ILP32 TLSDESC relocation support. There was existing MC support for ELF ILP32 relocations from D25159 which could be enabled by passing "-target-abi ilp32" to llvm-mc. This was changed to check for "gnu_ilp32" in the target triple instead. This shouldn't cause any issues since the existing support was slightly broken: it was generating ELF64 objects instead of the ELF32 object files expected by the GNU ILP32 toolchain. This target has been tested by running the full rustc testsuite on a big-endian ILP32 system based on the GCC ILP32 toolchain. Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D94143
38 lines
1.2 KiB
ArmAsm
38 lines
1.2 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-non-linux-gnu_ilp32 -filetype=obj \
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// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-ILP32 %s
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// RUN: llvm-mc -triple aarch64-non-linux-gnu -filetype=obj \
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// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-LP64 %s
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.text
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.file "../projects/clang/test/Driver/arm64-ilp32.c"
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.globl foo
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.align 2
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.type foo,@function
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foo: // @foo
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// %bb.0: // %entry
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sub sp, sp, #16 // =16
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// CHECK-ILP32: 00000004 R_AARCH64_P32_ADR_PREL_PG_HI21 sizes
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// CHECK-ILP32: 00000008 R_AARCH64_P32_ADD_ABS_LO12_NC sizes
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// CHECK-LP64: 0000000000000004 R_AARCH64_ADR_PREL_PG_HI21 sizes
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// CHECK-LP64: 0000000000000008 R_AARCH64_ADD_ABS_LO12_NC sizes
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adrp x8, sizes
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add x8, x8, :lo12:sizes
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str w0, [sp, #12]
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str w1, [sp, #8]
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ldr w0, [x8]
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add sp, sp, #16 // =16
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ret
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.Lfunc_end0:
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.size foo, .Lfunc_end0-foo
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.type sizes,@object // @sizes
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.data
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.globl sizes
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.align 2
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sizes:
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.word 1 // 0x1
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.word 2 // 0x2
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.word 4 // 0x4
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.word 4 // 0x4
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.word 4 // 0x4
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.size sizes, 20
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