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b5450e4ab7
Register context information was already being passed into the DWARFDebugFrame code that dumps unwind information but it wasn't being used. This change adds the ability to dump registers names of a valid MC register context was passed in and if it knows about the register. Updated the tests to use the newly returned register names. Differential Revision: https://reviews.llvm.org/D88767
102 lines
5.2 KiB
ArmAsm
102 lines
5.2 KiB
ArmAsm
// Test the bits of .eh_frame on mips that are already implemented correctly.
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips-unknown-linux-gnu
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS32 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF32,DWARF32_ABS %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mipsel-unknown-linux-gnu
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS32 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF32,DWARF32_ABS %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64el-unknown-linux-gnu
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
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/// Check that position-indenpendent code use PC-relative relocations:
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips-unknown-linux-gnu --position-independent
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC32 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF32,DWARF32_PIC %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mipsel-unknown-linux-gnu --position-independent
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC32 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF32,DWARF32_PIC %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu --position-independent
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64el-unknown-linux-gnu --position-independent
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s
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/// However using the large code model forces R_MIPS_64 since there is no R_MIPS_PC64 relocation:
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu --position-independent --large-code-model
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
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// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64el-unknown-linux-gnu --position-independent --large-code-model
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// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
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// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
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func:
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.cfi_startproc
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.cfi_endproc
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// RELOCS: Relocations [
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// RELOCS: Section ({{.+}}) .rel{{a?}}.eh_frame {
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// ABS32-NEXT: R_MIPS_32
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// ABS64-NEXT: R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE
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// PIC32-NEXT: R_MIPS_PC32
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// PIC64-NEXT: R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE
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// RELOCS-NEXT: }
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// DWARF32: 00000000 00000010 00000000 CIE
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// DWARF32-NEXT: Format: DWARF32
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// DWARF32-NEXT: Version: 1
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// DWARF32-NEXT: Augmentation: "zR"
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// DWARF32-NEXT: Code alignment factor: 1
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// DWARF32-NEXT: Data alignment factor: -4
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// DWARF32-NEXT: Return address column: 31
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// DWARF32_ABS-NEXT: Augmentation data: 0B
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// ^^ fde pointer encoding: DW_EH_PE_sdata4
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// DWARF32_PIC-NEXT: Augmentation data: 1B
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// ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4
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// DWARF32-EMPTY:
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// DWARF32-NEXT: DW_CFA_def_cfa_register: SP_64
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//
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// DWARF32_ABS: 00000014 00000010 00000018 FDE cie=00000000 pc=00000000...00000000
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// DWARF32_PIC: 00000014 00000010 00000018 FDE cie=00000000 pc=0000001c...0000001c
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// DWARF32-NEXT: Format: DWARF32
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// DWARF32-NEXT: DW_CFA_nop:
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// DWARF32-NEXT: DW_CFA_nop:
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// DWARF32-NEXT: DW_CFA_nop:
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// DWARF64: 00000000 00000010 00000000 CIE
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// DWARF64-NEXT: Format: DWARF32
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// DWARF64-NEXT: Version: 1
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// DWARF64-NEXT: Augmentation: "zR"
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// DWARF64-NEXT: Code alignment factor: 1
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// DWARF64-NEXT: Data alignment factor: -8
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// ^^ GAS uses -4. Should be ok as long as
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// all offsets we need are a multiple of 8.
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// DWARF64-NEXT: Return address column: 31
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// DWARF64_ABS-NEXT: Augmentation data: 0C
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// ^^ fde pointer encoding: DW_EH_PE_sdata8
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// DWARF64_PIC: Augmentation data: 1B
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// ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4
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// DWARF64-EMPTY:
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// DWARF64-NEXT: DW_CFA_def_cfa_register: SP_64
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// DWARF64_PIC-NEXT: DW_CFA_nop:
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//
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// DWARF64_ABS: 00000014 00000018 00000018 FDE cie=00000000 pc=00000000...00000000
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// DWARF64_PIC: 00000014 00000010 00000018 FDE cie=00000000 pc=00000000...00000000
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// DWARF64-NEXT: Format: DWARF32
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// DWARF64-NEXT: DW_CFA_nop:
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// DWARF64-NEXT: DW_CFA_nop:
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// DWARF64-NEXT: DW_CFA_nop:
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