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llvm-mirror/test/MC/VE/SRD.s
Kazushi (Jam) Marukawa db86191fa7 [VE] Support shift operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
shift operation instructions. Also change asmparser to support UImm7
operand. And, add new SLD/SRD/SLA instructions also.

Differential Revision: https://reviews.llvm.org/D81324
2020-06-08 10:19:14 +02:00

29 lines
987 B
ArmAsm

# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: srd %s11, %s11, %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x74]
srd %s11, %s11, %s11
# CHECK-INST: srd %s11, %s11, 63
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x74]
srd %s11, %s11, 63
# CHECK-INST: srd %s11, %s11, 127
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x74]
srd %s11, %s11, 127
# CHECK-INST: srd %s11, %s11, 64
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x74]
srd %s11, %s11, 64
# CHECK-INST: srd %s11, (32)1, 64
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x74]
srd %s11, (32)1, 64
# CHECK-INST: srd %s11, (32)0, 63
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x74]
srd %s11, (32)0, 63