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599ca91378
Summary: Avoids tons of prologue boilerplate when arguments are passed in memory and left in memory. This can happen in a debug build or in a release build when an argument alloca is escaped. This will dramatically affect the code size of x86 debug builds, because X86 fast isel doesn't handle arguments passed in memory at all. It only handles the x86_64 case of up to 6 basic register parameters. This is implemented by analyzing the entry block before ISel to identify copy elision candidates. A copy elision candidate is an argument that is used to fully initialize an alloca before any other possibly escaping uses of that alloca. If an argument is a copy elision candidate, we set a flag on the InputArg. If the the target generates loads from a fixed stack object that matches the size and alignment requirements of the alloca, the SelectionDAG builder will delete the stack object created for the alloca and replace it with the fixed stack object. The load is left behind to satisfy any remaining uses of the argument value. The store is now dead and is therefore elided. The fixed stack object is also marked as mutable, as it may now be modified by the user, and it would be invalid to rematerialize the initial load from it. Supersedes D28388 Fixes PR26328 Reviewers: chandlerc, MatzeB, qcolombet, inglorion, hans Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29668 llvm-svn: 296683
62 lines
1.4 KiB
LLVM
62 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=armv7-linux < %s | FileCheck %s
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declare arm_aapcscc void @addrof_i32(i32*)
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declare arm_aapcscc void @addrof_i64(i64*)
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define arm_aapcscc void @simple(i32, i32, i32, i32, i32 %x) {
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entry:
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%x.addr = alloca i32
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store i32 %x, i32* %x.addr
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call void @addrof_i32(i32* %x.addr)
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ret void
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}
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; CHECK-LABEL: simple:
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; CHECK: push {r11, lr}
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; CHECK: add r0, sp, #8
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; CHECK: bl addrof_i32
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; CHECK: pop {r11, pc}
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; We need to load %x before calling addrof_i32 now because it could mutate %x in
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; place.
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define arm_aapcscc i32 @use_arg(i32, i32, i32, i32, i32 %x) {
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entry:
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%x.addr = alloca i32
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store i32 %x, i32* %x.addr
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call void @addrof_i32(i32* %x.addr)
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ret i32 %x
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}
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; CHECK-LABEL: use_arg:
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; CHECK: push {[[csr:[^ ]*]], lr}
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; CHECK: ldr [[csr]], [sp, #8]
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; CHECK: add r0, sp, #8
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; CHECK: bl addrof_i32
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; CHECK: mov r0, [[csr]]
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; CHECK: pop {[[csr]], pc}
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define arm_aapcscc i64 @split_i64(i32, i32, i32, i32, i64 %x) {
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entry:
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%x.addr = alloca i64, align 4
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store i64 %x, i64* %x.addr, align 4
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call void @addrof_i64(i64* %x.addr)
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ret i64 %x
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}
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; CHECK-LABEL: split_i64:
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; CHECK: push {r4, r5, r11, lr}
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; CHECK: sub sp, sp, #8
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; CHECK: ldr r4, [sp, #28]
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; CHECK: ldr r5, [sp, #24]
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; CHECK: mov r0, sp
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; CHECK: str r4, [sp, #4]
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; CHECK: str r5, [sp]
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; CHECK: bl addrof_i64
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; CHECK: mov r0, r5
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; CHECK: mov r1, r4
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; CHECK: add sp, sp, #8
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; CHECK: pop {r4, r5, r11, pc}
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