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6c665bec7d
Summary: This patch adds support for the X asm constraint. To do this, we lower the constraint to either a "w" or "r" constraint depending on the operand type (both constraints are supported on ARM). Fixes PR26493 Reviewers: t.p.northover, echristo, rengolin Subscribers: joker.eph, jgreenhalgh, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19061 llvm-svn: 267411
22 lines
789 B
LLVM
22 lines
789 B
LLVM
; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfpv2 %s -o - | FileCheck %s -check-prefix=novfp
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; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefix=vfp
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; vfp-LABEL: f1
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; vfp-CHECK: vadd.f32 s0, s0, s0
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; In the novfp case, the compiler is forced to assign a core register.
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; Although this register class can't be used with the vadd.f32 instruction,
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; the compiler behaved as expected since it is allowed to emit anything.
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; novfp-LABEL: f1
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; novfp-CHECK: vadd.f32 r0, r0, r0
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; This can be generated by a function such as:
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; void f1(float f) {asm volatile ("add.f32 $0, $0, $0" : : "X" (f));}
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define arm_aapcs_vfpcc void @f1(float %f) {
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entry:
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call void asm sideeffect "vadd.f32 $0, $0, $0", "X" (float %f) nounwind
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ret void
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}
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