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5ccdb47717
In ARMPreAllocLoadStoreOpt::RescheduleOps, LastOp should be the last operation which we want to merge. If we break out of the loop because an operation has the wrong offset, we shouldn't use that operation as LastOp. This patch fixes some cases where we would move stores to the wrong insert point. Re-commit with a fix to increment NumMove in the right place. Differential Revision: https://reviews.llvm.org/D30124 llvm-svn: 296815
39 lines
1.4 KiB
LLVM
39 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=armv7--eabi -verify-machineinstrs < %s | FileCheck %s
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; Check the way we schedule/merge a bunch of loads and stores.
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; Originally test/CodeGen/ARM/2011-07-07-ScheduleDAGCrash.ll ; now
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; being used as a test of optimizations related to ldm/stm.
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; FIXME: We could merge more loads/stores with regalloc hints.
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; FIXME: Fix scheduling so we don't have 16 live registers.
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define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
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entry:
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%c = load i256, i256* %cc
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%d = load i256, i256* %dd
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%add = add nsw i256 %c, %d
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store i256 %add, i256* %a, align 8
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%or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
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%add6 = add nsw i256 %or, %d
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store i256 %add6, i256* %b, align 8
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ret void
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; CHECK-DAG: ldm r3
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; CHECK-DAG: ldm r2
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; CHECK-DAG: ldr {{.*}}, [r3, #20]
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; CHECK-DAG: ldr {{.*}}, [r3, #16]
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; CHECK-DAG: ldr {{.*}}, [r3, #28]
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; CHECK-DAG: ldr {{.*}}, [r3, #24]
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; CHECK-DAG: ldr {{.*}}, [r2, #20]
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; CHECK-DAG: ldr {{.*}}, [r2, #16]
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; CHECK-DAG: ldr {{.*}}, [r2, #28]
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; CHECK-DAG: ldr {{.*}}, [r2, #24]
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; CHECK-DAG: stmib r0
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; CHECK-DAG: str {{.*}}, [r0]
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; CHECK-DAG: str {{.*}}, [r0, #24]
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; CHECK-DAG: str {{.*}}, [r0, #28]
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; CHECK-DAG: str {{.*}}, [r1]
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; CHECK-DAG: stmib r1
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; CHECK-DAG: str {{.*}}, [r1, #24]
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; CHECK-DAG: str {{.*}}, [r1, #28]
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}
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