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There is not an official documented ABI for frame pointers in Thumb2, but we should try to emit something which is useful. We use r7 as the frame pointer for Thumb code, which currently means that if a function needs to save a high register (r8-r11), it will get pushed to the stack between the frame pointer (r7) and link register (r14). This means that while a stack unwinder can follow the chain of frame pointers up the stack, it cannot know the offset to lr, so does not know which functions correspond to the stack frames. To fix this, we need to push the callee-saved registers in two batches, with the first push saving the low registers, fp and lr, and the second push saving the high registers. This is already implemented, but previously only used for iOS. This patch turns it on for all Thumb2 targets when frame pointers are required by the ABI, and the frame pointer is r7 (Windows uses r11, so this isn't a problem there). If frame pointer elimination is enabled we still emit a single push/pop even if we need a frame pointer for other reasons, to avoid increasing code size. We must also ensure that lr is pushed to the stack when using a frame pointer, so that we end up with a complete frame record. Situations that could cause this were rare, because we already push lr in most situations so that we can return using the pop instruction. Differential Revision: https://reviews.llvm.org/D23516 llvm-svn: 279506
153 lines
4.6 KiB
LLVM
153 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -o - %s | FileCheck %s
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%struct = type { i8, i64, i8, double, i8, <2 x float>, i8, <4 x float> }
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define i32 @test_i64_align() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_i64_align:
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; CHECL: movs r0, #8
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ret i32 ptrtoint(i64* getelementptr(%struct, %struct* null, i32 0, i32 1) to i32)
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}
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define i32 @test_f64_align() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_f64_align:
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; CHECL: movs r0, #24
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ret i32 ptrtoint(double* getelementptr(%struct, %struct* null, i32 0, i32 3) to i32)
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}
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define i32 @test_v2f32_align() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_v2f32_align:
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; CHECL: movs r0, #40
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ret i32 ptrtoint(<2 x float>* getelementptr(%struct, %struct* null, i32 0, i32 5) to i32)
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}
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define i32 @test_v4f32_align() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_v4f32_align:
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; CHECL: movs r0, #64
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ret i32 ptrtoint(<4 x float>* getelementptr(%struct, %struct* null, i32 0, i32 7) to i32)
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}
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; Key point here is than an extra register has to be saved so that the DPRs end
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; up in an aligned location (as prologue/epilogue inserter had calculated).
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define void @test_dpr_unwind_align() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_dpr_unwind_align:
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; CHECK: push {r5, r6, r7, lr}
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; CHECK-NOT: sub sp
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; CHECK: vpush {d8, d9}
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; CHECK: .cfi_offset d9, -24
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; CHECK: .cfi_offset d8, -32
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; [...]
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; CHECK: bl _test_i64_align
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; CHECK-NOT: add sp,
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; CHECK: vpop {d8, d9}
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; CHECK-NOT: add sp,
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; CHECK: pop {r5, r6, r7, pc}
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call void asm sideeffect "", "~{r6},~{d8},~{d9}"()
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; Whatever
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call i32 @test_i64_align()
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ret void
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}
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; This time, there's no viable way to tack CS-registers onto the list: a real SP
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; adjustment needs to be performed to put d8 and d9 where they should be.
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define void @test_dpr_unwind_align_manually() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_dpr_unwind_align_manually:
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; CHECK: push {r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp
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; CHECK: push.w {r8, r11}
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; CHECK: sub sp, #4
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; CHECK: vpush {d8, d9}
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; CHECK: .cfi_offset d9, -40
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; CHECK: .cfi_offset d8, -48
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; [...]
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; CHECK: bl _test_i64_align
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; CHECK-NOT: add sp,
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; CHECK: vpop {d8, d9}
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; CHECK: add sp, #4
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; CHECK: pop.w {r8, r11}
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; CHECK: pop {r4, r5, r6, r7, pc}
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{d8},~{d9}"()
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; Whatever
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call i32 @test_i64_align()
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ret void
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}
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; If there's only a CS1 area, the sub should be in the right place:
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define void @test_dpr_unwind_align_just_cs1() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_dpr_unwind_align_just_cs1:
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; CHECK: push {r4, r5, r6, r7, lr}
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; CHECK: sub sp, #4
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; CHECK: vpush {d8, d9}
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; CHECK: .cfi_offset d9, -32
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; CHECK: .cfi_offset d8, -40
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; CHECK: sub sp, #8
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; [...]
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; CHECK: bl _test_i64_align
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; CHECK: add sp, #8
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; CHECK: vpop {d8, d9}
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; CHECK: add sp, #4
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; CHECK: pop {r4, r5, r6, r7, pc}
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{d8},~{d9}"()
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; Whatever
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call i32 @test_i64_align()
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ret void
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}
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; If there are no DPRs, we shouldn't try to align the stack in stages anyway
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define void @test_dpr_unwind_align_no_dprs() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_dpr_unwind_align_no_dprs:
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; CHECK: push {r4, r5, r6, r7, lr}
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; CHECK: sub sp, #12
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; [...]
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; CHECK: bl _test_i64_align
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; CHECK: add sp, #12
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; CHECK: pop {r4, r5, r6, r7, pc}
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7}"()
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; Whatever
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call i32 @test_i64_align()
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ret void
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}
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; 128-bit vectors should use 128-bit (i.e. correctly aligned) slots on
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; the stack.
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define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_v128_stack_pass:
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; CHECK: add r[[ADDR:[0-9]+]], sp, #16
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; CHECK: vld1.64 {d0, d1}, [r[[ADDR]]:128]
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ret <4 x float> %in
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}
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declare void @varargs(i32, ...)
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; When varargs are enabled, we go down a different route. Still want 128-bit
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; alignment though.
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define void @test_v128_stack_pass_varargs(<4 x float> %in) "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_v128_stack_pass_varargs:
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; CHECK: add r[[ADDR:[0-9]+]], sp, #16
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; CHECK: vst1.64 {d0, d1}, [r[[ADDR]]:128]
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call void(i32, ...) @varargs(i32 undef, [3 x i32] undef, float undef, <4 x float> %in)
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ret void
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}
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; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give
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; a single pointer), 64-bit quantities must be pass
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define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test_64bit_gpr_align:
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; CHECK: ldr [[RHS:r[0-9]+]], [sp]
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; CHECK: adds r0, [[RHS]], r2
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; CHECK: adc r1, r3, #0
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%ext = zext i32 %sp to i64
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%sum = add i64 %ext, %r2_r3
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ret i64 %sum
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}
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