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d8d28772c9
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector. Reviewers: delena, zvi Reviewed By: zvi Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30533 llvm-svn: 296856
443 lines
12 KiB
YAML
443 lines
12 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
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--- |
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define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
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%ret = add i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
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%ret = add i32 %arg1, %arg2
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ret i32 %ret
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}
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define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
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%ret = sub i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
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%ret = sub i32 %arg1, %arg2
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ret i32 %ret
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}
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define float @test_add_float(float %arg1, float %arg2) {
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%ret = fadd float %arg1, %arg2
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ret float %ret
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}
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define double @test_add_double(double %arg1, double %arg2) {
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%ret = fadd double %arg1, %arg2
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ret double %ret
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}
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define float @test_sub_float(float %arg1, float %arg2) {
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%ret = fsub float %arg1, %arg2
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ret float %ret
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}
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define double @test_sub_double(double %arg1, double %arg2) {
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%ret = fsub double %arg1, %arg2
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ret double %ret
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}
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define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = add <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = sub <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%ret = fadd <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%ret = fsub <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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...
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---
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name: test_add_i64
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr64 }
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# ALL-NEXT: - { id: 1, class: gr64 }
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# ALL-NEXT: - { id: 2, class: gr64 }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0 = COPY %rdi
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# ALL-NEXT: %1 = COPY %rsi
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# ALL-NEXT: %2 = ADD64rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s64) = COPY %rdi
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%1(s64) = COPY %rsi
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%2(s64) = G_ADD %0, %1
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...
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---
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name: test_add_i32
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr32 }
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# ALL-NEXT: - { id: 1, class: gr32 }
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# ALL-NEXT: - { id: 2, class: gr32 }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0 = COPY %edi
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# ALL-NEXT: %1 = COPY %esi
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# ALL-NEXT: %2 = ADD32rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s32) = COPY %edi
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%1(s32) = COPY %esi
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%2(s32) = G_ADD %0, %1
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...
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---
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name: test_sub_i64
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr64 }
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# ALL-NEXT: - { id: 1, class: gr64 }
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# ALL-NEXT: - { id: 2, class: gr64 }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0 = COPY %rdi
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# ALL-NEXT: %1 = COPY %rsi
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# ALL-NEXT: %2 = SUB64rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s64) = COPY %rdi
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%1(s64) = COPY %rsi
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%2(s64) = G_SUB %0, %1
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...
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---
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name: test_sub_i32
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr32 }
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# ALL-NEXT: - { id: 1, class: gr32 }
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# ALL-NEXT: - { id: 2, class: gr32 }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0 = COPY %edi
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# ALL-NEXT: %1 = COPY %esi
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# ALL-NEXT: %2 = SUB32rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s32) = COPY %edi
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%1(s32) = COPY %esi
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%2(s32) = G_SUB %0, %1
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...
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---
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name: test_add_float
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512F-NEXT: - { id: 0, class: fr32 }
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# NO_AVX512F-NEXT: - { id: 1, class: fr32 }
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# NO_AVX512F-NEXT: - { id: 2, class: fr32 }
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# AVX512ALL-NEXT: - { id: 0, class: fr32x }
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# AVX512ALL-NEXT: - { id: 1, class: fr32x }
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# AVX512ALL-NEXT: - { id: 2, class: fr32x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = ADDSSrr %0, %1
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# AVX-NEXT: %2 = VADDSSrr %0, %1
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# AVX512F-NEXT: %2 = VADDSSZrr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(s32) = COPY %xmm0
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%1(s32) = COPY %xmm1
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%2(s32) = G_FADD %0, %1
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%xmm0 = COPY %2(s32)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_double
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512F-NEXT: - { id: 0, class: fr64 }
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# NO_AVX512F-NEXT: - { id: 1, class: fr64 }
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# NO_AVX512F-NEXT: - { id: 2, class: fr64 }
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# AVX512ALL-NEXT: - { id: 0, class: fr64x }
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# AVX512ALL-NEXT: - { id: 1, class: fr64x }
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# AVX512ALL-NEXT: - { id: 2, class: fr64x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = ADDSDrr %0, %1
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# AVX-NEXT: %2 = VADDSDrr %0, %1
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# AVX512F-NEXT: %2 = VADDSDZrr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(s64) = COPY %xmm0
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%1(s64) = COPY %xmm1
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%2(s64) = G_FADD %0, %1
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%xmm0 = COPY %2(s64)
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RET 0, implicit %xmm0
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...
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---
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name: test_sub_float
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512F-NEXT: - { id: 0, class: fr32 }
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# NO_AVX512F-NEXT: - { id: 1, class: fr32 }
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# NO_AVX512F-NEXT: - { id: 2, class: fr32 }
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# AVX512ALL-NEXT: - { id: 0, class: fr32x }
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# AVX512ALL-NEXT: - { id: 1, class: fr32x }
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# AVX512ALL-NEXT: - { id: 2, class: fr32x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = SUBSSrr %0, %1
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# AVX-NEXT: %2 = VSUBSSrr %0, %1
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# AVX512F-NEXT: %2 = VSUBSSZrr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(s32) = COPY %xmm0
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%1(s32) = COPY %xmm1
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%2(s32) = G_FSUB %0, %1
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%xmm0 = COPY %2(s32)
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RET 0, implicit %xmm0
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...
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---
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name: test_sub_double
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512F-NEXT: - { id: 0, class: fr64 }
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# NO_AVX512F-NEXT: - { id: 1, class: fr64 }
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# NO_AVX512F-NEXT: - { id: 2, class: fr64 }
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# AVX512ALL-NEXT: - { id: 0, class: fr64x }
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# AVX512ALL-NEXT: - { id: 1, class: fr64x }
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# AVX512ALL-NEXT: - { id: 2, class: fr64x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = SUBSDrr %0, %1
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# AVX-NEXT: %2 = VSUBSDrr %0, %1
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# AVX512F-NEXT: %2 = VSUBSDZrr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(s64) = COPY %xmm0
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%1(s64) = COPY %xmm1
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%2(s64) = G_FSUB %0, %1
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%xmm0 = COPY %2(s64)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
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# AVX512VL-NEXT: - { id: 0, class: vr128x }
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# AVX512VL-NEXT: - { id: 1, class: vr128x }
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# AVX512VL-NEXT: - { id: 2, class: vr128x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = PADDDrr %0, %1
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# AVX-NEXT: %2 = VPADDDrr %0, %1
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# AVX512F-NEXT: %2 = VPADDDrr %0, %1
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# AVX512VL-NEXT: %2 = VPADDDZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = COPY %xmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<4 x s32>) = G_ADD %0, %1
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%xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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name: test_sub_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
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# AVX512VL-NEXT: - { id: 0, class: vr128x }
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# AVX512VL-NEXT: - { id: 1, class: vr128x }
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# AVX512VL-NEXT: - { id: 2, class: vr128x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = PSUBDrr %0, %1
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# AVX-NEXT: %2 = VPSUBDrr %0, %1
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# AVX512F-NEXT: %2 = VPSUBDrr %0, %1
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# AVX512VL-NEXT: %2 = VPSUBDZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = COPY %xmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<4 x s32>) = G_SUB %0, %1
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%xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_v4f32
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
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# AVX512VL-NEXT: - { id: 0, class: vr128x }
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# AVX512VL-NEXT: - { id: 1, class: vr128x }
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# AVX512VL-NEXT: - { id: 2, class: vr128x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = ADDPSrr %0, %1
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# AVX-NEXT: %2 = VADDPSrr %0, %1
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# AVX512F-NEXT: %2 = VADDPSrr %0, %1
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# AVX512VL-NEXT: %2 = VADDPSZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = COPY %xmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<4 x s32>) = G_FADD %0, %1
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%xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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name: test_sub_v4f32
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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# ALL: registers:
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# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
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# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
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# AVX512VL-NEXT: - { id: 0, class: vr128x }
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# AVX512VL-NEXT: - { id: 1, class: vr128x }
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# AVX512VL-NEXT: - { id: 2, class: vr128x }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %0 = COPY %xmm0
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# ALL-NEXT: %1 = COPY %xmm1
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# SSE-NEXT: %2 = SUBPSrr %0, %1
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# AVX-NEXT: %2 = VSUBPSrr %0, %1
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# AVX512F-NEXT: %2 = VSUBPSrr %0, %1
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# AVX512VL-NEXT: %2 = VSUBPSZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = COPY %xmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<4 x s32>) = G_FSUB %0, %1
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%xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit %xmm0
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...
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