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16c1c3ddfc
"insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
38 lines
1.1 KiB
LLVM
38 lines
1.1 KiB
LLVM
; PR28852: Check machine code sinking is not stopped by SUBREG_TO_REG.
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK: foo
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; CHECK-NOT: imull
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; CHECK: retq
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; CHECK: imull
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define void @foo(i64 %value, i32 %kLengthBits, i32* nocapture %bits, i64* nocapture %bit_buffer_64, i32 %x) local_unnamed_addr {
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entry:
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%mul = mul i32 %x, %kLengthBits
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%add = add i32 %mul, 3
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%conv = zext i32 %add to i64
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%mul2 = mul nuw nsw i64 %conv, 5
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%sub = sub i64 64, %value
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%conv4 = trunc i64 %sub to i32
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%tmp0 = load i32, i32* %bits, align 4
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%cmp = icmp ult i32 %tmp0, %conv4
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br i1 %cmp, label %if.then, label %if.end, !prof !0
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if.then: ; preds = %entry
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%add7 = add i64 %mul2, %value
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%tmp1 = load i64, i64* %bit_buffer_64, align 8
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%add8 = add i64 %add7, %tmp1
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store i64 %add8, i64* %bit_buffer_64, align 8
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%conv9 = trunc i64 %mul2 to i32
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store i32 %conv9, i32* %bits, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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!0 = !{!"branch_weights", i32 1, i32 2000}
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