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5c8adde3a4
We should probably teach the two address instruction pass to turn masked moves into BLENDM when its beneficial to the register allocator. llvm-svn: 291371
196 lines
8.4 KiB
LLVM
196 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -mattr=+avx512vl --show-mc-encoding| FileCheck %s
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define <32 x i8> @test_256_1(i8 * %addr) {
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; CHECK-LABEL: test_256_1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu (%rdi), %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%res = load <32 x i8>, <32 x i8>* %vaddr, align 1
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ret <32 x i8>%res
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}
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define void @test_256_2(i8 * %addr, <32 x i8> %data) {
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; CHECK-LABEL: test_256_2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu %ymm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x7f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <32 x i8>*
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store <32 x i8>%data, <32 x i8>* %vaddr, align 1
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ret void
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}
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define <32 x i8> @test_256_3(i8 * %addr, <32 x i8> %old, <32 x i8> %mask1) {
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; CHECK-LABEL: test_256_3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xef,0xd2]
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; CHECK-NEXT: vpcmpneqb %ymm2, %ymm1, %k1 ## encoding: [0x62,0xf3,0x75,0x28,0x3f,0xca,0x04]
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; CHECK-NEXT: vmovdqu8 (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf1,0x7f,0x29,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <32 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%r = load <32 x i8>, <32 x i8>* %vaddr, align 1
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%res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> %old
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ret <32 x i8>%res
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}
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define <32 x i8> @test_256_4(i8 * %addr, <32 x i8> %mask1) {
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; CHECK-LABEL: test_256_4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %ymm1, %ymm1, %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xef,0xc9]
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; CHECK-NEXT: vpcmpneqb %ymm1, %ymm0, %k1 ## encoding: [0x62,0xf3,0x7d,0x28,0x3f,0xc9,0x04]
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; CHECK-NEXT: vmovdqu8 (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0xa9,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <32 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%r = load <32 x i8>, <32 x i8>* %vaddr, align 1
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%res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> zeroinitializer
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ret <32 x i8>%res
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}
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define <16 x i16> @test_256_5(i8 * %addr) {
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; CHECK-LABEL: test_256_5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu (%rdi), %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%res = load <16 x i16>, <16 x i16>* %vaddr, align 1
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ret <16 x i16>%res
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}
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define void @test_256_6(i8 * %addr, <16 x i16> %data) {
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; CHECK-LABEL: test_256_6:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu %ymm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfe,0x7f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <16 x i16>*
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store <16 x i16>%data, <16 x i16>* %vaddr, align 1
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ret void
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}
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define <16 x i16> @test_256_7(i8 * %addr, <16 x i16> %old, <16 x i16> %mask1) {
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; CHECK-LABEL: test_256_7:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xef,0xd2]
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; CHECK-NEXT: vpcmpneqw %ymm2, %ymm1, %k1 ## encoding: [0x62,0xf3,0xf5,0x28,0x3f,0xca,0x04]
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; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf1,0xff,0x29,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <16 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%r = load <16 x i16>, <16 x i16>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> %old
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ret <16 x i16>%res
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}
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define <16 x i16> @test_256_8(i8 * %addr, <16 x i16> %mask1) {
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; CHECK-LABEL: test_256_8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %ymm1, %ymm1, %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xef,0xc9]
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; CHECK-NEXT: vpcmpneqw %ymm1, %ymm0, %k1 ## encoding: [0x62,0xf3,0xfd,0x28,0x3f,0xc9,0x04]
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; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xff,0xa9,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <16 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%r = load <16 x i16>, <16 x i16>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> zeroinitializer
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ret <16 x i16>%res
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}
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define <16 x i8> @test_128_1(i8 * %addr) {
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; CHECK-LABEL: test_128_1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%res = load <16 x i8>, <16 x i8>* %vaddr, align 1
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ret <16 x i8>%res
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}
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define void @test_128_2(i8 * %addr, <16 x i8> %data) {
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; CHECK-LABEL: test_128_2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <16 x i8>*
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store <16 x i8>%data, <16 x i8>* %vaddr, align 1
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ret void
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}
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define <16 x i8> @test_128_3(i8 * %addr, <16 x i8> %old, <16 x i8> %mask1) {
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; CHECK-LABEL: test_128_3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xef,0xd2]
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; CHECK-NEXT: vpcmpneqb %xmm2, %xmm1, %k1 ## encoding: [0x62,0xf3,0x75,0x08,0x3f,0xca,0x04]
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; CHECK-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf1,0x7f,0x09,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <16 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%r = load <16 x i8>, <16 x i8>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> %old
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ret <16 x i8>%res
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}
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define <16 x i8> @test_128_4(i8 * %addr, <16 x i8> %mask1) {
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; CHECK-LABEL: test_128_4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xef,0xc9]
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; CHECK-NEXT: vpcmpneqb %xmm1, %xmm0, %k1 ## encoding: [0x62,0xf3,0x7d,0x08,0x3f,0xc9,0x04]
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; CHECK-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0x89,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <16 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%r = load <16 x i8>, <16 x i8>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> zeroinitializer
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ret <16 x i8>%res
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}
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define <8 x i16> @test_128_5(i8 * %addr) {
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; CHECK-LABEL: test_128_5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%res = load <8 x i16>, <8 x i16>* %vaddr, align 1
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ret <8 x i16>%res
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}
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define void @test_128_6(i8 * %addr, <8 x i16> %data) {
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; CHECK-LABEL: test_128_6:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqu %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%vaddr = bitcast i8* %addr to <8 x i16>*
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store <8 x i16>%data, <8 x i16>* %vaddr, align 1
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ret void
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}
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define <8 x i16> @test_128_7(i8 * %addr, <8 x i16> %old, <8 x i16> %mask1) {
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; CHECK-LABEL: test_128_7:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xef,0xd2]
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; CHECK-NEXT: vpcmpneqw %xmm2, %xmm1, %k1 ## encoding: [0x62,0xf3,0xf5,0x08,0x3f,0xca,0x04]
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; CHECK-NEXT: vmovdqu16 (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf1,0xff,0x09,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <8 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%r = load <8 x i16>, <8 x i16>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> %old
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ret <8 x i16>%res
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}
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define <8 x i16> @test_128_8(i8 * %addr, <8 x i16> %mask1) {
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; CHECK-LABEL: test_128_8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xef,0xc9]
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; CHECK-NEXT: vpcmpneqw %xmm1, %xmm0, %k1 ## encoding: [0x62,0xf3,0xfd,0x08,0x3f,0xc9,0x04]
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; CHECK-NEXT: vmovdqu16 (%rdi), %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xff,0x89,0x6f,0x07]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%mask = icmp ne <8 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%r = load <8 x i16>, <8 x i16>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> zeroinitializer
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ret <8 x i16>%res
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}
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