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https://github.com/RPCS3/llvm-mirror.git
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f9745b3ea5
Summary: When conditional branches with complex conditions are split into multiple branches in SelectionDAGBuilder::FindMergedConditions, also handle inverted conditions. These may sometimes appear without having been optimized by InstCombine when CodeGenPrepare decides to sink and duplicate cmp instructions, causing them to have only one use. This problem can be increased by e.g. GVNHoist hiding more cmps from InstCombine by combining equivalent cmps from different blocks. For example codegen X & !(Y | Z) as: jmp_if_X TmpBB jmp FBB TmpBB: jmp_if_notY Tmp2BB jmp FBB Tmp2BB: jmp_if_notZ TBB jmp FBB Reviewers: bogner, MatzeB, qcolombet Subscribers: llvm-commits, hiraditya, mcrosier, sebpop Differential Revision: https://reviews.llvm.org/D28380 llvm-svn: 292944
174 lines
5.6 KiB
LLVM
174 lines
5.6 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -disable-cgp-select2branch | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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entry:
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; CHECK-LABEL: test1:
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; CHECK: btl
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: cmovael (%rcx), %eax
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; CHECK-NEXT: ret
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%0 = lshr i32 %x, %n ; <i32> [#uses=1]
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%1 = and i32 %0, 1 ; <i32> [#uses=1]
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%toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
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%v = load i32, i32* %vp
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%.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
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ret i32 %.0
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}
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define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: btl
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: cmovbl (%rcx), %eax
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; CHECK-NEXT: ret
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%0 = lshr i32 %x, %n ; <i32> [#uses=1]
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%1 = and i32 %0, 1 ; <i32> [#uses=1]
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%toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
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%v = load i32, i32* %vp
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%.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1]
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ret i32 %.0
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}
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; x86's 32-bit cmov zeroes the high 32 bits of the destination. Make
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; sure CodeGen takes advantage of that to avoid an unnecessary
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; zero-extend (movl) after the cmov.
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declare void @bar(i64) nounwind
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define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: cmov{{n?}}el %[[R1:e..]], %[[R2:e..]]
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; CHECK-NOT: movl
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; CHECK: call
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%c = trunc i64 %a to i32
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%d = trunc i64 %b to i32
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%e = select i1 %p, i32 %c, i32 %d
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%f = zext i32 %e to i64
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call void @bar(i64 %f)
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ret void
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}
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; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
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; move without recomputing EFLAGS, because the expansion of the conditional
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; move with control flow may clobber EFLAGS (e.g., with xor, to set the
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; register to zero).
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; The test is a little awkward; the important part is that there's a test before the
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; setne.
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; PR4814
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@g_3 = external global i8 ; <i8*> [#uses=1]
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@g_96 = external global i8 ; <i8*> [#uses=2]
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@g_100 = external global i8 ; <i8*> [#uses=2]
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@_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1]
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define i1 @test4() nounwind {
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entry:
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%0 = load i8, i8* @g_3, align 1 ; <i8> [#uses=2]
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%1 = sext i8 %0 to i32 ; <i32> [#uses=1]
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%.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1]
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%tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1]
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%tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1]
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%iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1]
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%retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
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%2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2]
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%g_96.promoted.i = load i8, i8* @g_96 ; <i8> [#uses=3]
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%3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2]
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br i1 %3, label %func_4.exit.i, label %bb.i.i.i
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bb.i.i.i: ; preds = %entry
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%4 = load volatile i8, i8* @g_100, align 1 ; <i8> [#uses=0]
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br label %func_4.exit.i
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; CHECK-LABEL: test4:
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; CHECK: g_100
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; CHECK: testb
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; CHECK-NOT: xor
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; CHECK: setne
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; CHECK: testb
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func_4.exit.i: ; preds = %bb.i.i.i, %entry
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%.not.i = xor i1 %2, true ; <i1> [#uses=1]
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%brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1]
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%.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1]
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br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
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bb.i.i: ; preds = %func_4.exit.i
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%5 = load volatile i8, i8* @g_100, align 1 ; <i8> [#uses=0]
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br label %func_1.exit
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func_1.exit: ; preds = %bb.i.i, %func_4.exit.i
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%g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
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%ret = phi i1 [ 0, %bb.i.i ], [ %.not.i, %func_4.exit.i ]
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store i8 %g_96.tmp.0.i, i8* @g_96
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%6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1]
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%7 = tail call i32 (i8*, ...) @printf(i8* noalias getelementptr ([15 x i8], [15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
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ret i1 %ret
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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; Should compile to setcc | -2.
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; rdar://6668608
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define i32 @test5(i32* nocapture %P) nounwind readonly {
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entry:
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; CHECK-LABEL: test5:
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; CHECK: xorl %eax, %eax
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; CHECK: setg %al
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; CHECK: orl $-2, %eax
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; CHECK: ret
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%0 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
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%1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1]
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ret i32 %iftmp.0.0
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}
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define i32 @test6(i32* nocapture %P) nounwind readonly {
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entry:
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; CHECK-LABEL: test6:
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; CHECK: xorl %eax, %eax
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; CHECK: setl %al
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; CHECK: leal 4(%rax,%rax,8), %eax
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; CHECK: ret
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%0 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
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%1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1]
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ret i32 %iftmp.0.0
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}
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; Don't try to use a 16-bit conditional move to do an 8-bit select,
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; because it isn't worth it. Just use a branch instead.
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define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: testb $1, %dil
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; CHECK-NEXT: jne LBB
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%d = select i1 %c, i8 %a, i8 %b
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ret i8 %d
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}
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define i32 @smin(i32 %x) {
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; CHECK-LABEL: smin:
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; CHECK: ## BB#0:
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; CHECK-NEXT: xorl $-1, %edi
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovsl %edi, %eax
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; CHECK-NEXT: retq
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%not_x = xor i32 %x, -1
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%1 = icmp slt i32 %not_x, -1
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%sel = select i1 %1, i32 %not_x, i32 -1
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ret i32 %sel
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}
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