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The comment talked about replacing vpmovzxwd+vpslld+vpsrad with vpmovsxwd - which isn't valid as we're sign extending a <8 x i1> bool vector not an all/nobits <8 x i16> llvm-svn: 292948
15 lines
568 B
LLVM
15 lines
568 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s
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define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
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; CHECK-LABEL: foo:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
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; CHECK-NEXT: vpsrad $31, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%s = sext <8 x i1> %bar to <8 x i32>
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ret <8 x i32> %s
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}
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