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51f2170fda
There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
120 lines
4.8 KiB
LLVM
120 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VLDQ
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define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
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; AVX512VL-LABEL: v4f32:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512VL-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v4f32:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512VLDQ-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
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ret <4 x float> %tmp
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}
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define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
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; AVX512VL-LABEL: v8f32:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to8}, %ymm1, %ymm1
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to8}, %ymm0, %ymm0
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; AVX512VL-NEXT: vpor %ymm1, %ymm0, %ymm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v8f32:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to8}, %ymm1, %ymm1
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to8}, %ymm0, %ymm0
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; AVX512VLDQ-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
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ret <8 x float> %tmp
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}
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define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
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; AVX512VL-LABEL: v16f32:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm1, %zmm1
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; AVX512VL-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; AVX512VL-NEXT: vporq %zmm1, %zmm0, %zmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v16f32:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to16}, %zmm1, %zmm1
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; AVX512VLDQ-NEXT: vorps %zmm1, %zmm0, %zmm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <16 x float> @llvm.copysign.v16f32( <16 x float> %a, <16 x float> %b )
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ret <16 x float> %tmp
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}
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define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
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; AVX512VL-LABEL: v2f64:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX512VL-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v2f64:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
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; AVX512VLDQ-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX512VLDQ-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
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ret <2 x double> %tmp
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}
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define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
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; AVX512VL-LABEL: v4f64:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm1, %ymm1
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; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm0
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; AVX512VL-NEXT: vpor %ymm1, %ymm0, %ymm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v4f64:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to4}, %ymm1, %ymm1
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; AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
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; AVX512VLDQ-NEXT: vorpd %ymm1, %ymm0, %ymm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )
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ret <4 x double> %tmp
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}
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define <8 x double> @v8f64(<8 x double> %a, <8 x double> %b) nounwind {
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; AVX512VL-LABEL: v8f64:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; AVX512VL-NEXT: vporq %zmm1, %zmm0, %zmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512VLDQ-LABEL: v8f64:
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; AVX512VLDQ: ## BB#0:
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; AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; AVX512VLDQ-NEXT: vorpd %zmm1, %zmm0, %zmm0
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; AVX512VLDQ-NEXT: retq
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%tmp = tail call <8 x double> @llvm.copysign.v8f64( <8 x double> %a, <8 x double> %b )
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ret <8 x double> %tmp
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}
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declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
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declare <8 x float> @llvm.copysign.v8f32(<8 x float> %Mag, <8 x float> %Sgn)
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declare <16 x float> @llvm.copysign.v16f32(<16 x float> %Mag, <16 x float> %Sgn)
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declare <2 x double> @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)
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declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
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declare <8 x double> @llvm.copysign.v8f64(<8 x double> %Mag, <8 x double> %Sgn)
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