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llvm-mirror/test/CodeGen/X86/vec_set-D.ll
Simon Pilgrim 82e2b6d48e [X86][SSE] Fix domains for VZEXT_LOAD type instructions
Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions.

Differential Revision: https://reviews.llvm.org/D27684

llvm-svn: 289825
2016-12-15 16:05:29 +00:00

13 lines
451 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
define <4 x i32> @t(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: t:
; CHECK: # BB#0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: retl
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
%tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
ret <4 x i32> %tmp2
}