David Peixotto 569d73691e MC: support different sized constants in constant pools ... On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 llvm-svn: 213387		2014-07-18 16:05:14 +00:00
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AArch64	MC: support different sized constants in constant pools	2014-07-18 16:05:14 +00:00
ARM	MC: support different sized constants in constant pools	2014-07-18 16:05:14 +00:00
AsmParser	Allow using .cfi_startproc without a leading symbol.	2014-06-23 15:34:32 +00:00
COFF	MC: Let non-temporary COFF aliases be in symtab	2014-07-13 04:31:19 +00:00
Disassembler	[X86] AVX512: Add disassembler support for compressed displacement	2014-07-17 17:04:56 +00:00
ELF	Avoid revocations when possible.	2014-07-01 14:34:30 +00:00
MachO	llvm-readobj: fix MachO relocatoin printing a bit.	2014-07-04 10:57:56 +00:00
Markup
Mips	[mips] .reginfo is 8 byte aligned on N32.	2014-07-17 10:10:04 +00:00
PowerPC	Emit DWARF3 call frame information when DWARF3+ debug info is requested	2014-06-19 15:39:33 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	MC: fix MCAsmInfo usage for windows-itanium	2014-07-17 16:27:40 +00:00