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e6c7dc68db
The pipeliner needs to remove instructions from the SlotIndexes structure when they are deleted. Otherwise, the SlotIndexes map has stale data, and an assert will occur when adding new instructions. This patch also changes the pipeliner to make the back-edge of a loop carried dependence 1 cycle. The 1 cycle latency is added to the anti-dependence that represents the back-edge. This changes eliminates a couple of hacks added to the pipeliner to handle the latency of the back-edge. It is needed to correctly pipeline the test case for the sub-register elimination pass. llvm-svn: 328113
56 lines
2.2 KiB
LLVM
56 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon -rdf-opt=0 < %s | FileCheck %s
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; Test that we generate the correct name for a value in a prolog block. The
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; pipeliner was using an incorrect value for an instruction in the 2nd prolog
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; block for a value defined by a Phi. The result was that an instruction in
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; the 1st and 2nd prolog blocks contain the same operands.
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; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
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; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
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; CHECK: loop0
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define void @f0(<64 x i32> %a0, <32 x i32> %a1) #0 {
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b0:
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v0 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %a0)
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br label %b2
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b2: ; preds = %b4, %b1
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%v1 = phi <32 x i32> [ %a1, %b1 ], [ %v7, %b4 ]
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br label %b3
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b3: ; preds = %b3, %b2
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%v2 = phi i32 [ 0, %b2 ], [ %v8, %b3 ]
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%v3 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v0, %b3 ]
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%v4 = phi <32 x i32> [ %v1, %b2 ], [ %v7, %b3 ]
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%v5 = tail call <1024 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32> %v3, <32 x i32> undef)
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%v6 = tail call <1024 x i1> @llvm.hexagon.V6.veqh.and.128B(<1024 x i1> %v5, <32 x i32> undef, <32 x i32> undef)
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%v7 = tail call <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<1024 x i1> %v6, <32 x i32> %v4, <32 x i32> undef)
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%v8 = add nsw i32 %v2, 1
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%v9 = icmp slt i32 %v8, undef
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br i1 %v9, label %b3, label %b4
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b4: ; preds = %b3
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br i1 undef, label %b5, label %b2
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b5: ; preds = %b4, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <1024 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <1024 x i1> @llvm.hexagon.V6.veqh.and.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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