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c2af269623
In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
32 lines
971 B
LLVM
32 lines
971 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check for a successful compilation.
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; CHECK: jumpr r31
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define void @fred() #0 {
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b0:
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%v1 = icmp sgt <8 x i32> undef, undef
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%v2 = extractelement <8 x i1> %v1, i32 4
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%v3 = select i1 %v2, i32 0, i32 undef
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%v4 = add nsw i32 %v3, 0
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%v5 = add nsw i32 0, %v4
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%v6 = extractelement <8 x i1> %v1, i32 6
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%v7 = select i1 %v6, i32 0, i32 undef
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%v8 = add nsw i32 %v7, %v5
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%v9 = add nsw i32 0, %v8
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%v10 = add nsw i32 0, %v9
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%v11 = load i32, i32* undef, align 4
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%v12 = mul nsw i32 %v11, %v10
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%v13 = add nsw i32 %v12, 16384
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%v14 = ashr i32 %v13, 15
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%v15 = select i1 undef, i32 %v14, i32 255
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%v16 = trunc i32 %v15 to i8
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store i8 %v16, i8* undef, align 1
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ret void
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}
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attributes #0 = { norecurse nounwind }
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