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093adf3ff9
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. llvm-svn: 74420
60 lines
1.4 KiB
LLVM
60 lines
1.4 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm | grep {ldr r0} | count 7
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; RUN: llvm-as < %s | llc -march=arm | grep mov | grep 1
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; RUN: llvm-as < %s | llc -march=arm | not grep mvn
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; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsl
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; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsr
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define i32 @f1(i32* %v) {
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entry:
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%tmp = load i32* %v
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ret i32 %tmp
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}
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define i32 @f2(i32* %v) {
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entry:
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%tmp2 = getelementptr i32* %v, i32 1023
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%tmp = load i32* %tmp2
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ret i32 %tmp
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}
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define i32 @f3(i32* %v) {
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entry:
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%tmp2 = getelementptr i32* %v, i32 1024
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%tmp = load i32* %tmp2
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ret i32 %tmp
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}
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define i32 @f4(i32 %base) {
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entry:
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%tmp1 = sub i32 %base, 128
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%tmp2 = inttoptr i32 %tmp1 to i32*
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%tmp3 = load i32* %tmp2
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ret i32 %tmp3
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}
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define i32 @f5(i32 %base, i32 %offset) {
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entry:
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%tmp1 = add i32 %base, %offset
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%tmp2 = inttoptr i32 %tmp1 to i32*
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%tmp3 = load i32* %tmp2
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ret i32 %tmp3
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}
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define i32 @f6(i32 %base, i32 %offset) {
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entry:
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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%tmp4 = load i32* %tmp3
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ret i32 %tmp4
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}
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define i32 @f7(i32 %base, i32 %offset) {
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entry:
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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%tmp4 = load i32* %tmp3
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ret i32 %tmp4
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}
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