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6db76aaf10
This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
23 lines
902 B
LLVM
23 lines
902 B
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fldd | count 4
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fstd
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd
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define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
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entry:
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%0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
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%1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
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%2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
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%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
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store <2 x i32> %3, <2 x i32>* %r, align 8
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ret void
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}
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define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
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entry:
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%0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
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%1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
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%2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
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%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
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ret <2 x i32> %3
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}
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