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6db76aaf10
This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
24 lines
933 B
LLVM
24 lines
933 B
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vldmia | count 4
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vstmia | count 1
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd | count 2
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define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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entry:
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%0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
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%1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
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%2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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store <4 x i32> %3, <4 x i32>* %r, align 16
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ret void
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}
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define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
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entry:
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%0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
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%1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
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%2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %3
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}
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