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6db76aaf10
This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
54 lines
1.5 KiB
LLVM
54 lines
1.5 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vneg\\.s8} %t | count 2
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; RUN: grep {vneg\\.s16} %t | count 2
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; RUN: grep {vneg\\.s32} %t | count 2
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; RUN: grep {vneg\\.f32} %t | count 2
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define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <4 x float> %tmp2
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}
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