mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-30 23:42:52 +01:00
da9360e77e
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> llvm-svn: 62990
24 lines
709 B
LLVM
24 lines
709 B
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
|
; RUN: grep fceq %t1.s | count 1
|
|
; RUN: grep fcmeq %t1.s | count 1
|
|
|
|
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
|
target triple = "spu"
|
|
|
|
; Exercise the floating point comparison operators for f32:
|
|
|
|
declare double @fabs(double)
|
|
declare float @fabsf(float)
|
|
|
|
define i1 @fcmp_eq(float %arg1, float %arg2) {
|
|
%A = fcmp oeq float %arg1, %arg2
|
|
ret i1 %A
|
|
}
|
|
|
|
define i1 @fcmp_mag_eq(float %arg1, float %arg2) {
|
|
%1 = call float @fabsf(float %arg1)
|
|
%2 = call float @fabsf(float %arg2)
|
|
%3 = fcmp oeq float %1, %2
|
|
ret i1 %3
|
|
}
|