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llvm-mirror/test/CodeGen/Mips/2008-07-23-fpcmp.ll
Dan Gohman 5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00

35 lines
946 B
LLVM

; RUN: llvm-as < %s | llc -march=mips -f -o %t
; RUN: grep {c\\..*\\.s} %t | count 3
; RUN: grep {bc1\[tf\]} %t | count 3
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-psp-elf"
define float @A(float %a, float %b) nounwind {
entry:
fcmp ogt float %a, 1.000000e+00 ; <i1>:0 [#uses=1]
br i1 %0, label %bb, label %bb2
bb: ; preds = %entry
fadd float %a, 1.000000e+00 ; <float>:1 [#uses=1]
ret float %1
bb2: ; preds = %entry
ret float %b
}
define float @B(float %a, float %b) nounwind {
entry:
fcmp ogt float %a, 1.000000e+00 ; <i1>:0 [#uses=1]
%.0 = select i1 %0, float %a, float %b ; <float> [#uses=1]
ret float %.0
}
define i32 @C(i32 %a, i32 %b, float %j) nounwind {
entry:
fcmp ogt float %j, 1.000000e+00 ; <i1>:0 [#uses=1]
%.0 = select i1 %0, i32 %a, i32 %b ; <i32> [#uses=1]
ret i32 %.0
}