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86275193d3
Summary: This makes is possible to have R600RegisterInfo and SIRegisterInfo not inherit from AMDGPURegisterInfo. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46280 llvm-svn: 331490
88 lines
2.7 KiB
C++
88 lines
2.7 KiB
C++
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIRegisterInfo.h"
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using namespace llvm;
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AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
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static const unsigned SubRegs[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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AMDGPU::sub15
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};
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assert(Channel < array_lengthof(SubRegs));
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return SubRegs[Channel];
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}
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void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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MCRegAliasIterator R(Reg, this, true);
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for (; R.isValid(); ++R)
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Reserved.set(*R);
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}
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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// Forced to be here by one .inc
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const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
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const MachineFunction *MF) const {
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CallingConv::ID CC = MF->getFunction().getCallingConv();
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switch (CC) {
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case CallingConv::C:
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case CallingConv::Fast:
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case CallingConv::Cold:
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return CSR_AMDGPU_HighRegs_SaveList;
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default: {
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// Dummy to not crash RegisterClassInfo.
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static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
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return &NoCalleeSavedReg;
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}
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}
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}
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const MCPhysReg *
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SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
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return nullptr;
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}
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const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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switch (CC) {
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case CallingConv::C:
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case CallingConv::Fast:
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case CallingConv::Cold:
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return CSR_AMDGPU_HighRegs_RegMask;
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default:
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return nullptr;
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}
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}
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unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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return FuncInfo->getFrameOffsetReg();
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}
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