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e47439baae
- Argument attribute needs specifiying through `ArgIndex<n>` (corresponding to `FirstArgIndex`) to distinguish explicitly from the index number from the overloaded type list. - In addition, `RetIndex` (corresponding to `ReturnIndex`) and `FuncIndex` (corresponding to `FunctionIndex`) are introduced for us to associate attributes on the return value and potentially function itself. Differential Revision: https://reviews.llvm.org/D80422
69 lines
3.2 KiB
TableGen
69 lines
3.2 KiB
TableGen
//===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the RISCV-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Atomics
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// Atomic Intrinsics have multiple versions for different access widths, which
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// all follow one of the following signatures (depending on how many arguments
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// they require). We carefully instantiate only specific versions of these for
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// specific integer widths, rather than using `llvm_anyint_ty`.
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//
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// In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the
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// canonical names, and the intrinsics used in the code will have a name
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// suffixed with the pointer type they are specialised for (denoted `<p>` in the
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// names below), in order to avoid type conflicts.
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let TargetPrefix = "riscv" in {
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// T @llvm.<name>.T.<p>(any*, T, T, T imm);
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class MaskedAtomicRMWFourArg<LLVMType itype>
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: Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
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// T @llvm.<name>.T.<p>(any*, T, T, T, T imm);
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class MaskedAtomicRMWFiveArg<LLVMType itype>
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: Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype, itype],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<4>>]>;
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// We define 32-bit and 64-bit variants of the above, where T stands for i32
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// or i64 respectively:
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multiclass MaskedAtomicRMWFourArgIntrinsics {
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// i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm);
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def _i32 : MaskedAtomicRMWFourArg<llvm_i32_ty>;
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// i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm);
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def _i64 : MaskedAtomicRMWFourArg<llvm_i64_ty>;
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}
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multiclass MaskedAtomicRMWFiveArgIntrinsics {
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// i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32, i32 imm);
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def _i32 : MaskedAtomicRMWFiveArg<llvm_i32_ty>;
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// i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm);
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def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>;
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}
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// @llvm.riscv.masked.atomicrmw.*.{i32,i64}.<p>(...)
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defm int_riscv_masked_atomicrmw_xchg : MaskedAtomicRMWFourArgIntrinsics;
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defm int_riscv_masked_atomicrmw_add : MaskedAtomicRMWFourArgIntrinsics;
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defm int_riscv_masked_atomicrmw_sub : MaskedAtomicRMWFourArgIntrinsics;
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defm int_riscv_masked_atomicrmw_nand : MaskedAtomicRMWFourArgIntrinsics;
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// Signed min and max need an extra operand to do sign extension with.
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defm int_riscv_masked_atomicrmw_max : MaskedAtomicRMWFiveArgIntrinsics;
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defm int_riscv_masked_atomicrmw_min : MaskedAtomicRMWFiveArgIntrinsics;
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// Unsigned min and max don't need the extra operand.
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defm int_riscv_masked_atomicrmw_umax : MaskedAtomicRMWFourArgIntrinsics;
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defm int_riscv_masked_atomicrmw_umin : MaskedAtomicRMWFourArgIntrinsics;
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// @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
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defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
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} // TargetPrefix = "riscv"
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