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Summary: MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction and register defintions, which are huge so we only want to include them where needed. This will also make it easier if we want to split the R600 and GCN definitions into separate tablegenerated files. I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h because it uses some enums from the header to initialize default values for the SIMachineFunction class, so I ended up having to remove includes of SIMachineFunctionInfo.h from headers too. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46272 llvm-svn: 332930
168 lines
5.5 KiB
C++
168 lines
5.5 KiB
C++
//===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// i1 values are usually inserted by the CFG Structurize pass and they are
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/// unique in that they can be copied from VALU to SALU registers.
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/// This is not possible for any other value type. Since there are no
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/// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
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///
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//===----------------------------------------------------------------------===//
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//
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#define DEBUG_TYPE "si-i1-copies"
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPULaneDominator.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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namespace {
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class SILowerI1Copies : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SILowerI1Copies() : MachineFunctionPass(ID) {
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initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Lower i1 Copies"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SILowerI1Copies, DEBUG_TYPE,
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"SI Lower i1 Copies", false, false)
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char SILowerI1Copies::ID = 0;
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char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
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FunctionPass *llvm::createSILowerI1CopiesPass() {
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return new SILowerI1Copies();
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}
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bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
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std::vector<unsigned> I1Defs;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
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unsigned Reg = MI.getOperand(0).getReg();
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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if (RC == &AMDGPU::VReg_1RegClass)
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MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
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continue;
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}
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if (MI.getOpcode() != AMDGPU::COPY)
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continue;
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const MachineOperand &Dst = MI.getOperand(0);
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const MachineOperand &Src = MI.getOperand(1);
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if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) ||
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!TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
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continue;
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
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DebugLoc DL = MI.getDebugLoc();
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MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg());
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if (DstRC == &AMDGPU::VReg_1RegClass &&
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TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
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I1Defs.push_back(Dst.getReg());
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if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
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if (DefInst->getOperand(1).isImm()) {
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I1Defs.push_back(Dst.getReg());
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int64_t Val = DefInst->getOperand(1).getImm();
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assert(Val == 0 || Val == -1);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
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.add(Dst)
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.addImm(Val);
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MI.eraseFromParent();
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continue;
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}
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}
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unsigned int TmpSrc = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::COPY), TmpSrc)
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.add(Src);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
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.add(Dst)
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.addImm(0)
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.addImm(-1)
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.addReg(TmpSrc);
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MI.eraseFromParent();
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} else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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SrcRC == &AMDGPU::VReg_1RegClass) {
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if (DefInst->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
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DefInst->getOperand(1).isImm() && DefInst->getOperand(2).isImm() &&
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DefInst->getOperand(1).getImm() == 0 &&
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DefInst->getOperand(2).getImm() != 0 &&
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DefInst->getOperand(3).isReg() &&
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TargetRegisterInfo::isVirtualRegister(
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DefInst->getOperand(3).getReg()) &&
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TRI->getCommonSubClass(
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MRI.getRegClass(DefInst->getOperand(3).getReg()),
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&AMDGPU::SGPR_64RegClass) &&
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AMDGPU::laneDominates(DefInst->getParent(), &MBB)) {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64))
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.add(Dst)
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.addReg(AMDGPU::EXEC)
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.add(DefInst->getOperand(3));
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} else {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64))
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.add(Dst)
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.add(Src)
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.addImm(0);
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}
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MI.eraseFromParent();
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}
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}
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}
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for (unsigned Reg : I1Defs)
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MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
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return false;
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}
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