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081c2ca61f
This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
41 lines
907 B
CMake
41 lines
907 B
CMake
set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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GlobalISelEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp
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SubtargetEmitter.cpp
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SubtargetFeatureInfo.cpp
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TableGen.cpp
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Types.cpp
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X86DisassemblerTables.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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CTagsEmitter.cpp
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)
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