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a515fb7c17
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
32 lines
1.3 KiB
LLVM
32 lines
1.3 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @sint_to_fp_v2i32
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; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
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; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
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; SI-CHECK: @sint_to_fp_v2i32
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; SI-CHECK: V_CVT_F32_I32_e32
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; SI-CHECK: V_CVT_F32_I32_e32
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define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
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%result = sitofp <2 x i32> %in to <2 x float>
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store <2 x float> %result, <2 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @sint_to_fp_v4i32
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; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: @sint_to_fp_v4i32
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; SI-CHECK: V_CVT_F32_I32_e32
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; SI-CHECK: V_CVT_F32_I32_e32
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; SI-CHECK: V_CVT_F32_I32_e32
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; SI-CHECK: V_CVT_F32_I32_e32
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define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%value = load <4 x i32> addrspace(1) * %in
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%result = sitofp <4 x i32> %value to <4 x float>
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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