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When running under LTO, it is common to not specify the architecture spec, which is used for setting up the target machine, and instead rely on features specified in each function to generate the correct instructions. This works for the code generator, but the RISC-V backend uses the AsmPrinter to do instruction compression, which does not see these features but instead uses a MCSubtargetInfo object to see whether compression is enabled. Since this is configured based on the TargetMachine at startup, it will result in compressed instructions not being emitted when it has not been given the 'c' TargetFeature, but the function has it. This changes the RISCVAsmPrinter to re-initialize the STI feature set based on the current MachineFunction, such that compressed instructions are now correctly emitted regardless of the method used to enable them. Differential revision: https://reviews.llvm.org/D73339 |
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Analysis | ||
Assembler | ||
Bindings | ||
Bitcode | ||
BugPoint | ||
CodeGen | ||
DebugInfo | ||
Demangle | ||
Examples | ||
ExecutionEngine | ||
Feature | ||
FileCheck | ||
Instrumentation | ||
Integer | ||
JitListener | ||
Linker | ||
LTO | ||
MachineVerifier | ||
MC | ||
Object | ||
ObjectYAML | ||
Other | ||
Reduce | ||
SafepointIRVerifier | ||
Support | ||
SymbolRewriter | ||
TableGen | ||
ThinLTO/X86 | ||
tools | ||
Transforms | ||
Unit | ||
Verifier | ||
YAMLParser | ||
.clang-format | ||
CMakeLists.txt | ||
lit.cfg.py | ||
lit.site.cfg.py.in | ||
TestRunner.sh |