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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 12:43:36 +01:00
llvm-mirror/test/CodeGen
Mikael Holmen 57aa13d4fa [MIR] Change test case to read from stdin instead of file
The

    ;CHECK: bb
    ;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0

parts of the test case failed when the tests were placed in a directory
including "bb" in the path, since the full path of the file is then
output in the
 ; ModuleID = '/repo/bb/
line which the CHECK matched on and then the CHECK-NEXT failed.

llvm-svn: 371171
2019-09-06 06:55:54 +00:00
..
AArch64 GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints 2019-09-06 00:05:58 +00:00
AMDGPU AMDGPU/GlobalISel: Fix load/store of types in other address spaces 2019-09-06 00:36:06 +00:00
ARC
ARM [IfConversion] Fix diamond conversion with unanalyzable branches. 2019-09-05 20:02:38 +00:00
AVR
BPF
Generic
Hexagon [Hexagon] Fix type in HexagonTargetLowering::ReplaceNodeResults 2019-09-05 16:19:47 +00:00
Inputs
Lanai
Mips [MIPS GlobalISel] Select G_FENCE 2019-09-05 11:20:32 +00:00
MIR [MIR] Change test case to read from stdin instead of file 2019-09-06 06:55:54 +00:00
MSP430
NVPTX
PowerPC
RISCV
SPARC
SystemZ
Thumb
Thumb2 [ARM] Fixup the creation of VPT blocks 2019-09-05 13:37:04 +00:00
WebAssembly
WinCFGuard
WinEH
X86 [X86] Add tests for extending and truncating between v16i8 and v16i64 with min-legal-vector-width=256. 2019-09-06 06:02:17 +00:00
XCore