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8727650a31
Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. NOTE: re-commit by fixing a failure in Codegen/AMDGPU/llvm.dbg.value.ll Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256282
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.SI.tid() nounwind readnone
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; SI-LABEL: {{^}}foo:
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; SI: .section .AMDGPU.csdata
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; SI: ; Kernel info:
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; SI: ; NumSgprs: {{[0-9]+}}
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; SI: ; NumVgprs: {{[0-9]+}}
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define void @foo(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %abase, i32 addrspace(1)* %bbase) nounwind {
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%tid = call i32 @llvm.SI.tid() nounwind readnone
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%aptr = getelementptr i32, i32 addrspace(1)* %abase, i32 %tid
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%bptr = getelementptr i32, i32 addrspace(1)* %bbase, i32 %tid
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%outptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%b = load i32, i32 addrspace(1)* %bptr, align 4
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %outptr, align 4
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ret void
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}
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; SI-LABEL: {{^}}one_vgpr_used:
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; SI: NumVgprs: 1
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define void @one_vgpr_used(i32 addrspace(1)* %out, i32 %x) nounwind {
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store i32 %x, i32 addrspace(1)* %out, align 4
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ret void
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}
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