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14ec8add52
Most of these are system instructions or other instructions we don't use in CodeGen. No point wasting space for them in the table. Removing them from the autogenerated table makes it easier to review the manual table. A few are real opcode collisions where the memory and register forms are completely different instructions. llvm-svn: 334474
89 lines
3.5 KiB
TableGen
89 lines
3.5 KiB
TableGen
//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel VMX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VMX instructions
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let SchedRW = [WriteSystem] in {
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// 66 0F 38 80
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def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
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"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[Not64BitMode]>;
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def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
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"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[In64BitMode]>;
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// 66 0F 38 81
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def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
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"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[Not64BitMode]>;
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def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
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"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[In64BitMode]>;
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// 0F 01 C1
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def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
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def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
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"vmclear\t$vmcs", []>, PD;
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// OF 01 D4
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def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
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// 0F 01 C2
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def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
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// 0F 01 C3
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def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
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def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
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"vmptrld\t$vmcs", []>, PS;
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def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs),
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"vmptrst\t$vmcs", []>, PS;
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def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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let mayStore = 1 in {
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def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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} // mayStore
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def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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let mayLoad = 1 in {
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def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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} // mayLoad
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// 0F 01 C4
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def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
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def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
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"vmxon\t$vmxon", []>, XS;
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} // SchedRW
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