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https://github.com/RPCS3/llvm-mirror.git
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39b5a7c2bb
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
42 lines
933 B
CMake
42 lines
933 B
CMake
set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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GlobalISelEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp
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SubtargetEmitter.cpp
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SubtargetFeatureInfo.cpp
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TableGen.cpp
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Types.cpp
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X86DisassemblerTables.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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CTagsEmitter.cpp
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)
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