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f56c09c87f
If a resource can be held for multiple cycles in the schedule model then an instruction can be placed into the available queue, another instruction can be scheduled, but the first will not be taken back out if the two instructions hazard. To fix this make sure that we update the available queue even on the first MOp of a cycle, pushing available instructions back into the pending queue if they now conflict. This happens with some downstream schedules we have around MVE instruction scheduling where we use ResourceCycles=[2] to show the instruction executing over two beats. Apparently the test changes here are OK too. Differential Revision: https://reviews.llvm.org/D76909
27 lines
992 B
LLVM
27 lines
992 B
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
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define i32 @foo() nounwind {
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entry:
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; CHECK: cntlzw 3, 3
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%retval = alloca i32, align 4 ; <i32*> [#uses=2]
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%temp = alloca i32, align 4 ; <i32*> [#uses=2]
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%ctz_x = alloca i32, align 4 ; <i32*> [#uses=3]
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%ctz_c = alloca i32, align 4 ; <i32*> [#uses=2]
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store i32 61440, i32* %ctz_x
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%tmp = load i32, i32* %ctz_x ; <i32> [#uses=1]
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%tmp1 = sub i32 0, %tmp ; <i32> [#uses=1]
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%tmp2 = load i32, i32* %ctz_x ; <i32> [#uses=1]
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%tmp3 = and i32 %tmp1, %tmp2 ; <i32> [#uses=1]
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%tmp4 = call i32 asm "$(cntlz$|cntlzw$) $0,$1", "=r,r,~{dirflag},~{fpsr},~{flags}"( i32 %tmp3 ) ; <i32> [#uses=1]
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store i32 %tmp4, i32* %ctz_c
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%tmp5 = load i32, i32* %ctz_c ; <i32> [#uses=1]
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store i32 %tmp5, i32* %temp
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%tmp6 = load i32, i32* %temp ; <i32> [#uses=1]
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store i32 %tmp6, i32* %retval
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br label %return
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return: ; preds = %entry
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%retval2 = load i32, i32* %retval ; <i32> [#uses=1]
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ret i32 %retval2
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}
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