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llvm-mirror/test/CodeGen/PowerPC/PR33671.ll
Jay Foad 3f23d4b8c3 [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
tryLatency compares two sched candidates. For the top zone it prefers
the one with lesser depth, but only if that depth is greater than the
total latency of the instructions we've already scheduled -- otherwise
its latency would be hidden and there would be no stall.

Unfortunately it only tests the depth of one of the candidates. This can
lead to situations where the TopDepthReduce heuristic does not kick in,
but a lower priority heuristic chooses the other candidate, whose depth
*is* greater than the already scheduled latency, which causes a stall.

The fix is to apply the heuristic if the depth of *either* candidate is
greater than the already scheduled latency.

All this also applies to the BotHeightReduce heuristic in the bottom
zone.

Differential Revision: https://reviews.llvm.org/D72392
2020-07-17 11:02:13 +01:00

33 lines
1.2 KiB
LLVM

; Function Attrs: norecurse nounwind
; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 < %s | FileCheck %s
define void @test1(i32* nocapture readonly %arr, i32* nocapture %arrTo) {
entry:
%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 4
%0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 4
%1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 16
store <4 x i32> %2, <4 x i32>* %0, align 16
ret void
; CHECK-LABEL: test1
; CHECK: lxv [[LD:[0-9]+]], 16(3)
; CHECK: stxv [[LD]], 16(4)
}
; Function Attrs: norecurse nounwind
define void @test2(i32* nocapture readonly %arr, i32* nocapture %arrTo) {
entry:
%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
%0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 16
store <4 x i32> %2, <4 x i32>* %0, align 16
ret void
; CHECK-LABEL: test2
; CHECK: addi 3, 3, 8
; CHECK: addi [[REG:[0-9]+]], 4, 4
; CHECK: lxvx [[LD:[0-9]+]], 0, 3
; CHECK: stxvx [[LD]], 0, [[REG]]
}