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032393eea9
For the below case, pre-inc prep think it's a good candidate to use pre-inc for the bucket, but 64bit integer load/store update (pre-inc) instruction on Power requires the displacement field should be DS-form (4's multiple). Since it can't satisfy the constraint, we have to do some fix ups later. As below, the original load/stores could be well-form, it makes things worse.
unsigned long long result = 0;
unsigned long long foo(char *p, unsigned long long n) {
for (unsigned long long i = 0; i < n; i++) {
unsigned long long x1 = *(unsigned long long *)(p - 50000 + i);
unsigned long long x2 = *(unsigned long long *)(p - 61024 + i);
unsigned long long x3 = *(unsigned long long *)(p - 62048 + i);
unsigned long long x4 = *(unsigned long long *)(p - 64096 + i);
result *= x1 * x2 * x3 * x4;
}
return result;
}
Patch by jedilyn(Kewen Lin).
Differential Revision: https://reviews.llvm.org/D48813
--This line, and those below, will be ignored--
M lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
A test/CodeGen/PowerPC/preincprep-i64-check.ll
llvm-svn: 336074
125 lines
4.5 KiB
LLVM
125 lines
4.5 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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; Verify pre-inc preparation pass doesn't prepare pre-inc for i64 load/store
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; when the stride doesn't conform LDU/STDU DS-form requirement.
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@result = local_unnamed_addr global i64 0, align 8
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define i64 @test_preinc_i64_ld(i8* nocapture readonly, i64) local_unnamed_addr {
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%3 = icmp eq i64 %1, 0
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br i1 %3, label %4, label %6
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; <label>:4: ; preds = %2
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%5 = load i64, i64* @result, align 8
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br label %13
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; <label>:6: ; preds = %2
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%7 = getelementptr inbounds i8, i8* %0, i64 -50000
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%8 = getelementptr inbounds i8, i8* %0, i64 -61024
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%9 = getelementptr inbounds i8, i8* %0, i64 -62048
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%10 = getelementptr inbounds i8, i8* %0, i64 -64096
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%11 = load i64, i64* @result, align 8
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br label %15
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; <label>:12: ; preds = %15
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store i64 %33, i64* @result, align 8
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br label %13
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; <label>:13: ; preds = %12, %4
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%14 = phi i64 [ %5, %4 ], [ %33, %12 ]
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ret i64 %14
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; <label>:15: ; preds = %15, %6
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%16 = phi i64 [ %11, %6 ], [ %33, %15 ]
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%17 = phi i64 [ 0, %6 ], [ %34, %15 ]
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%18 = getelementptr inbounds i8, i8* %7, i64 %17
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%19 = bitcast i8* %18 to i64*
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%20 = load i64, i64* %19, align 8
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%21 = getelementptr inbounds i8, i8* %8, i64 %17
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%22 = bitcast i8* %21 to i64*
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%23 = load i64, i64* %22, align 8
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%24 = getelementptr inbounds i8, i8* %9, i64 %17
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%25 = bitcast i8* %24 to i64*
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%26 = load i64, i64* %25, align 8
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%27 = getelementptr inbounds i8, i8* %10, i64 %17
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%28 = bitcast i8* %27 to i64*
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%29 = load i64, i64* %28, align 8
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%30 = mul i64 %23, %20
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%31 = mul i64 %30, %26
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%32 = mul i64 %31, %29
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%33 = mul i64 %32, %16
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%34 = add nuw i64 %17, 1
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%35 = icmp eq i64 %34, %1
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br i1 %35, label %12, label %15
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}
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; CHECK-LABEL: test_preinc_i64_ld
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -11023
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -12047
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -14095
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; CHECK-DAG: ld {{[0-9]+}}, 14096([[REG1:[0-9]+]])
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; CHECK-DAG: ld {{[0-9]+}}, 3072([[REG1]])
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; CHECK-DAG: ld {{[0-9]+}}, 2048([[REG1]])
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; CHECK-DAG: ld {{[0-9]+}}, 0([[REG1]])
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; CHECK: blr
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define i64 @test_preinc_i64_ldst(i8* nocapture, i64, i64) local_unnamed_addr {
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%4 = icmp eq i64 %1, 0
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br i1 %4, label %5, label %7
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; <label>:5: ; preds = %3
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%6 = load i64, i64* @result, align 8
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br label %16
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; <label>:7: ; preds = %3
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%8 = add i64 %2, 1
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%9 = getelementptr inbounds i8, i8* %0, i64 -1024
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%10 = add i64 %2, 2
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%11 = getelementptr inbounds i8, i8* %0, i64 -2048
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%12 = getelementptr inbounds i8, i8* %0, i64 -3072
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%13 = getelementptr inbounds i8, i8* %0, i64 -4096
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%14 = load i64, i64* @result, align 8
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br label %18
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; <label>:15: ; preds = %18
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store i64 %32, i64* @result, align 8
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br label %16
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; <label>:16: ; preds = %15, %5
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%17 = phi i64 [ %6, %5 ], [ %32, %15 ]
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ret i64 %17
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; <label>:18: ; preds = %18, %7
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%19 = phi i64 [ %14, %7 ], [ %32, %18 ]
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%20 = phi i64 [ 0, %7 ], [ %33, %18 ]
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%21 = getelementptr inbounds i8, i8* %9, i64 %20
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%22 = bitcast i8* %21 to i64*
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store i64 %8, i64* %22, align 8
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%23 = getelementptr inbounds i8, i8* %11, i64 %20
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%24 = bitcast i8* %23 to i64*
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store i64 %10, i64* %24, align 8
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%25 = getelementptr inbounds i8, i8* %12, i64 %20
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%26 = bitcast i8* %25 to i64*
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%27 = load i64, i64* %26, align 8
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%28 = getelementptr inbounds i8, i8* %13, i64 %20
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%29 = bitcast i8* %28 to i64*
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%30 = load i64, i64* %29, align 8
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%31 = mul i64 %30, %27
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%32 = mul i64 %31, %19
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%33 = add nuw i64 %20, 1
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%34 = icmp eq i64 %33, %1
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br i1 %34, label %15, label %18
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}
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; CHECK-LABEL: test_preinc_i64_ldst
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -3071
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -2047
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; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, -1023
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; CHECK-DAG: ld {{[0-9]+}}, -1024([[REG2:[0-9]+]])
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; CHECK-DAG: ld {{[0-9]+}}, -2048([[REG2]])
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; CHECK-DAG: std {{[0-9]+}}, 1024([[REG2]])
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; CHECK-DAG: std {{[0-9]+}}, 0([[REG2]])
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