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7a5e15697d
The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
61 lines
2.2 KiB
LLVM
61 lines
2.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.amdgcn.rsq.f32(float) #0
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declare double @llvm.amdgcn.rsq.f64(double) #0
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; FUNC-LABEL: {{^}}rsq_f32:
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define void @rsq_f32(float addrspace(1)* %out, float %src) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
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store float %rsq, float addrspace(1)* %out, align 4
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ret void
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}
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; TODO: Really these should be constant folded
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; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0
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define void @rsq_f32_constant_4.0(float addrspace(1)* %out) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
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store float %rsq, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f32_constant_100.0
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; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000
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define void @rsq_f32_constant_100.0(float addrspace(1)* %out) #1 {
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%rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
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store float %rsq, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f64:
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @rsq_f64(double addrspace(1)* %out, double %src) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
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store double %rsq, double addrspace(1)* %out, align 4
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ret void
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}
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; TODO: Really these should be constant folded
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; FUNC-LABEL: {{^}}rsq_f64_constant_4.0
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 4.0
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define void @rsq_f64_constant_4.0(double addrspace(1)* %out) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double 4.0) #0
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store double %rsq, double addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_f64_constant_100.0
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; SI-DAG: s_mov_b32 s{{[0-9]+}}, 0x40590000
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; SI-DAG: s_mov_b32 s{{[0-9]+}}, 0{{$}}
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; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
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define void @rsq_f64_constant_100.0(double addrspace(1)* %out) #1 {
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%rsq = call double @llvm.amdgcn.rsq.f64(double 100.0) #0
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store double %rsq, double addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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