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ee6ca71f38
This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
35 lines
761 B
LLVM
35 lines
761 B
LLVM
; Check that modelling of CC/CCRegs does not stop MachineCSE from
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; removing a compare. MachineCSE will not extend a live range of an
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; allocatable or reserved phys reg.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @bar(i8)
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; Check the low end of the CH range.
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define void @f1(i32 %lhs) {
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; CHECK-LABEL: BB#1:
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; CHECK-NOT: cijlh %r0, 1, .LBB0_3
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entry:
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%and188 = and i32 %lhs, 255
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%cmp189 = icmp ult i32 %and188, 2
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br i1 %cmp189, label %if.then.191, label %if.else.201
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if.then.191:
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%cmp194 = icmp eq i32 %and188, 1
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br i1 %cmp194, label %if.then.196, label %if.else.198
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if.then.196:
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call void @bar(i8 1);
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br label %if.else.201
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if.else.198:
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call void @bar(i8 0);
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br label %if.else.201
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if.else.201:
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ret void
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}
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