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dc9a43dec1
This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
83 lines
2.6 KiB
LLVM
83 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=thumbv8m.base-eabi -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
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; RUN: llc -mtriple=thumbv7m-eabi -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
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; RUN: llc -mtriple=thumbv8m.main-eabi -arm-execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
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@var = global i32 0
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define i32 @global() minsize {
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; CHECK-LABEL: global:
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; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
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; CHECK: movt [[GLOBDEST]], :upper16:var
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%val = load i32, i32* @var
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ret i32 %val
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}
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define i32 @jump_table(i32 %c, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: jump_table:
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; CHECK-T2: adr.w [[REG_JT:r[0-9]+]], .LJTI1_0
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; CHECK-T2: add.w [[REG_ENTRY:r[0-9]+]], [[REG_JT]], {{r[0-9]+}}, lsl #2
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; CHECK-T2: mov pc, [[REG_ENTRY]]
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; CHECK-T2BASE: lsls [[REG_OFFSET:r[0-9]+]], {{r[0-9]+}}, #2
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; CHECK-T2BASE: adr [[REG_JT:r[0-9]+]], .LJTI1_0
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; CHECK-T2BASE: adds [[REG_ENTRY:r[0-9]+]], [[REG_OFFSET]], [[REG_JT]]
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; CHECK-T2BASE: mov pc, [[REG_ENTRY]]
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; CHECK-LABEL: .LJTI1_0:
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; CHECK-NEXT: b.w
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; CHECK-NEXT: b.w
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; CHECK-NEXT: b.w
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; CHECK-NEXT: b.w
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; CHECK-NEXT: b.w
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; CHECK-NEXT: b.w
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entry:
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switch i32 %c, label %return [
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i32 1, label %sw.bb
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i32 2, label %sw.bb1
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i32 3, label %sw.bb3
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i32 4, label %sw.bb4
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i32 5, label %sw.bb6
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i32 6, label %sw.bb8
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]
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sw.bb: ; preds = %entry
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%add = add nsw i32 %a, 6
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br label %return
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sw.bb1: ; preds = %entry
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%add2 = add nsw i32 %a, 4
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br label %return
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sw.bb3: ; preds = %entry
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%sub = add nsw i32 %a, -3
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br label %return
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sw.bb4: ; preds = %entry
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%add5 = add nsw i32 %b, 5
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br label %return
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sw.bb6: ; preds = %entry
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%add7 = add nsw i32 %a, 1
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br label %return
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sw.bb8: ; preds = %entry
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%add9 = add nsw i32 %a, 2
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br label %return
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return: ; preds = %entry, %sw.bb8, %sw.bb6, %sw.bb4, %sw.bb3, %sw.bb1, %sw.bb
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%retval.0 = phi i32 [ %add9, %sw.bb8 ], [ %add7, %sw.bb6 ], [ %add5, %sw.bb4 ], [ %sub, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ]
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ret i32 %retval.0
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}
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@.str = private unnamed_addr constant [4 x i8] c"FOO\00", align 1
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define hidden i8* @string_literal() {
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entry:
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; CHECK-LABEL: string_literal:
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; CHECK-NOT: .asciz
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; CHECK: .fnend
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ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0)
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}
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