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Commit rL290616 (https://reviews.llvm.org/rL290616) changed a checking command for the triple arm-apple-darwin in LLVM::CodeGen/ARM/fpcmp_ueq.ll. As a result of the changes the test could fail for the valid generated code. These changes fixes the test to check only instructions we would expect. Differential Revision: https://reviews.llvm.org/D28159 llvm-svn: 291678
26 lines
716 B
LLVM
26 lines
716 B
LLVM
; RUN: llc -mtriple arm-apple-darwin -filetype asm -o - %s | FileCheck -check-prefix CHECK-ARMv4 %s
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; RUN: llc -mtriple armv7-apple-darwin -mcpu=cortex-a8 -filetype asm -o - %s | FileCheck -check-prefix CHECK-ARMv7 %s
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define i32 @f7(float %a, float %b) {
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entry:
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%tmp = fcmp ueq float %a,%b
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%retval = select i1 %tmp, i32 666, i32 42
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ret i32 %retval
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}
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; CHECK-ARMv4-LABEL: f7:
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; CHECK-ARMv4-DAG: bl ___eqsf2
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; CHECK-ARMv4-DAG: bl ___unordsf2
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; CHECK-ARMv4: cmp r0, #0
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; CHECK-ARMv4: movne r0, #1
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; CHECK-ARMv4: orrs r0, r0,
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; CHECK-ARMv4: moveq r0, #42
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; CHECK-ARMv7-LABEL: f7:
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; CHECK-ARMv7: vcmpe.f32
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; CHECK-ARMv7: vmrs APSR_nzcv, fpscr
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; CHECK-ARMv7: movweq
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; CHECK-ARMv7-NOT: vmrs
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; CHECK-ARMv7: movwvs
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