Fraser Cormack 58a6d02787 [VP][SelectionDAG] Add a target-configurable EVL operand type ... This patch adds a way for the target to configure the type it uses for the explicit vector length operands of VP SDNodes. The type must be a legal integer type (there is still no target-independent legalization of this operand) and must currently be at least as big as i32, the type used by the IR intrinsics. An implicit zero-extension takes place on targets which choose a larger type. All VP nodes should be created with this type used for the EVL operand. This allows 64-bit RISC-V to avoid custom legalization of all VP nodes, keeping them in their target-independent form for that bit longer. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D103027		2021-05-27 15:27:36 +01:00
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llvm	[VP][SelectionDAG] Add a target-configurable EVL operand type	2021-05-27 15:27:36 +01:00
llvm-c	[ORC][C-bindings] Replace LLVMOrcJITTargetMachineBuilderDisposeTargetTriple.	2021-05-21 17:38:06 -07:00