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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
llvm-mirror/test/CodeGen
Manman Ren 2c236a30f6 X86 Peephole: fold loads to the source register operand if possible.
Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.

rdar://10554090 and rdar://11873276

llvm-svn: 161207
2012-08-02 19:37:32 +00:00
..
ARM Clear kill flags in removeCopyByCommutingDef(). 2012-07-31 02:47:24 +00:00
CellSPU Implement r160312 as target indepedenet dag combine. 2012-07-17 08:31:11 +00:00
CPP test commit 2012-07-18 17:53:05 +00:00
Generic Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed. 2012-07-15 20:39:08 +00:00
Hexagon
MBlaze
Mips Set transient stack alignment in constructor of MipsFrameLowering and re-enable 2012-08-02 18:15:13 +00:00
MSP430
NVPTX
PowerPC
SPARC test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines. 2012-07-03 04:29:20 +00:00
Thumb
Thumb2 [arm-fast-isel] Add support for vararg function calls. 2012-07-19 09:49:00 +00:00
X86 X86 Peephole: fold loads to the source register operand if possible. 2012-08-02 19:37:32 +00:00
XCore