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3af4859657
Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
222 lines
6.8 KiB
LLVM
222 lines
6.8 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-NOFPXX
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; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-FPXX
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NOFPXX
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FPXX
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; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-NOFPXX
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; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX
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; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NOFPXX
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; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips4 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX
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; RUN-TODO: llc -march=mips64 -mcpu=mips64 -mattr=-n64,+o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX
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declare double @dbl();
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; 4-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
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; 64-FPXX: LLVM ERROR: FPXX is not permitted for the N32/N64 ABI's.
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define double @test1(double %d, ...) {
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ret double %d
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; ALL-LABEL: test1:
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; 32-NOFPXX: mtc1 $4, $f0
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; 32-NOFPXX: mtc1 $5, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $4, 0($sp)
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; 32-FPXX: sw $5, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $4, $f0
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; 32R2-NOFPXX: mthc1 $5, $f0
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; 32R2-FPXX: mtc1 $4, $f0
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; 32R2-FPXX: mthc1 $5, $f0
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 4-NOFPXX: mov.d $f0, $f12
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; 64-NOFPXX: mov.d $f0, $f12
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}
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define double @test2(i32 %i, double %d) {
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ret double %d
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; ALL-LABEL: test2:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f13
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; 64-NOFPXX: mov.d $f0, $f13
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}
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define double @test3(float %f1, float %f2, double %d) {
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ret double %d
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; ALL-LABEL: test3:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f14
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; 64-NOFPXX: mov.d $f0, $f14
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}
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define double @test4(float %f, double %d, ...) {
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ret double %d
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; ALL-LABEL: test4:
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; 32-NOFPXX: mtc1 $6, $f0
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; 32-NOFPXX: mtc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $6, $f0
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; 32R2-NOFPXX: mthc1 $7, $f0
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; 32R2-FPXX: mtc1 $6, $f0
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; 32R2-FPXX: mthc1 $7, $f0
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; 4-NOFPXX: mov.d $f0, $f13
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; 64-NOFPXX: mov.d $f0, $f13
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}
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define double @test5() {
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ret double 0.000000e+00
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; ALL-LABEL: test5:
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; 32-NOFPXX: mtc1 $zero, $f0
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; 32-NOFPXX: mtc1 $zero, $f1
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $zero, 0($sp)
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; 32-FPXX: sw $zero, 4($sp)
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; 32-FPXX: ldc1 $f0, 0($sp)
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; 32R2-NOFPXX: mtc1 $zero, $f0
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; 32R2-NOFPXX: mthc1 $zero, $f0
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; 32R2-FPXX: mtc1 $zero, $f0
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; 32R2-FPXX: mthc1 $zero, $f0
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; 4-NOFPXX: dmtc1 $zero, $f0
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; 64-NOFPXX: dmtc1 $zero, $f0
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}
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define double @test6(double %a, double %b, ...) {
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%1 = fsub double %a, %b
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ret double %1
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; ALL-LABEL: test6:
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; 32-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32-NOFPXX-DAG: mtc1 $5, ${{f[0-9]*[13579]}}
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; 32-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32-NOFPXX-DAG: mtc1 $7, ${{f[0-9]*[13579]}}
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; 32-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32-FPXX: addiu $sp, $sp, -8
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; 32-FPXX: sw $6, 0($sp)
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; 32-FPXX: sw $7, 4($sp)
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; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
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; 32-FPXX: sw $4, 0($sp)
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; 32-FPXX: sw $5, 4($sp)
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; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
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; 32-FPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-NOFPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32R2-NOFPXX-DAG: mthc1 $5, $[[T0]]
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; 32R2-NOFPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32R2-NOFPXX-DAG: mthc1 $7, $[[T1]]
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; 32R2-NOFPXX: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-FPXX-DAG: mtc1 $4, $[[T0:f[0-9]+]]
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; 32R2-FPXX-DAG: mthc1 $5, $[[T0]]
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; 32R2-FPXX-DAG: mtc1 $6, $[[T1:f[0-9]+]]
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; 32R2-FPXX-DAG: mthc1 $7, $[[T1]]
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; 32R2-FPXX: sub.d $f0, $[[T0]], $[[T1]]
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 4-NOFPXX: sub.d $f0, $f12, $f13
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; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
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; 64-NOFPXX: sub.d $f0, $f12, $f13
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}
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define double @move_from1(double %d) {
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%1 = call double @dbl()
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%2 = call double @test2(i32 0, double %1)
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ret double %2
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; ALL-LABEL: move_from1:
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; 32-NOFPXX-DAG: mfc1 $6, $f0
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; 32-NOFPXX-DAG: mfc1 $7, $f1
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; 32-FPXX: addiu $sp, $sp, -32
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; 32-FPXX: sdc1 $f0, 16($sp)
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; 32-FPXX: lw $6, 16($sp)
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; FIXME: This store is redundant
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; 32-FPXX: sdc1 $f0, 16($sp)
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; 32-FPXX: lw $7, 20($sp)
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; 32R2-NOFPXX-DAG: mfc1 $6, $f0
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; 32R2-NOFPXX-DAG: mfhc1 $7, $f0
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; 32R2-FPXX-DAG: mfc1 $6, $f0
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; 32R2-FPXX-DAG: mfhc1 $7, $f0
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; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
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; We can't use inline assembly to force a copy either because trying to force
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; a copy to a GPR this way fails with ; "couldn't allocate input reg for
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; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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; in a simple test.
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; 4-NOFPXX: mov.d $f13, $f0
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; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
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; We can't use inline assembly to force a copy either because trying to force
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; a copy to a GPR this way fails with ; "couldn't allocate input reg for
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; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
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; in a simple test.
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; 64-NOFPXX: mov.d $f13, $f0
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}
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