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030e941124
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
28 lines
855 B
LLVM
28 lines
855 B
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@j = global i32 -5, align 4
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@k = global i32 10, align 4
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@l = global i32 20, align 4
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@m = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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@.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
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define void @test() nounwind {
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entry:
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%0 = load i32* @k, align 4
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%1 = load i32* @j, align 4
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%cmp = icmp sge i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move $[[REGISTER:[0-9]+]], $24
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; 16: xor $[[REGISTER]], ${{[0-9]+}}
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%2 = load i32* @m, align 4
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%cmp1 = icmp sge i32 %0, %2
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @r2, align 4
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ret void
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}
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